NDLI: Functional ECO using metal-configurable gate-array spare cells

Content Provider	IEEE Xplore Digital Library
Author	Hua-Yu Chang Jiang, I.H.-R. Yao-Wen Chang
Copyright Year	2014
Description	Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Jiang, I.H.-R.) \|\| Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Hua-Yu Chang; Yao-Wen Chang)
Abstract	Metal-configurable gate-array spare cells, which have versatile functionality, are developed to overcome the inflexibility of standard spare cells used in conventional metal-only engineering change order (ECO). In this paper, we focus on functional ECO optimization using the new type of spare cells to fully exploit its strength. We observe that this functional ECO problem has the nature of dynamic logical and physical costs for selecting spare gate arrays. Unlike existing functional ECO works, which perform technology mapping based on ECO patches, we perform reverse mapping from spare gate arrays to handle these dynamic costs. We devise a spare array relation graph to record geometrical adjacency among spare gate arrays and interleave with the and-inverter network of ECO patches. To avoid redundant traversal and monitor the dynamic costs, we adopt A* search to simultaneously traverse and map between the logical ECO network and the physical spare array relation graph.
Starting Page	1
Ending Page	6
File Size	1137514
Page Count	6
File Format	PDF
ISBN	9781479930173
DOI	10.1145/2593069.2593145
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic arrays Logic gates Silicon Standards Optimization Libraries Wiring Technology mapping Engineering change order Gate array
Content Type	Text
Resource Type	Article

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