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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhenkun Yang Kecheng Hao Kai Cong Li Lei Ray, S. Fei Xie |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Comput. Sci., Portland State Univ., Portland, OR, USA (Zhenkun Yang; Kecheng Hao; Kai Cong; Li Lei; Fei Xie) || Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA (Ray, S.) |
| Abstract | Behavioral synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/SystemC) into a register-transfer level (RTL) implementation. In this paper, we present a scalable equivalence checking framework to validate the correctness of compiler transformations employed by behavioral synthesis front-end. Our approach makes use of dual-rail symbolic simulation of the input and output of a transformation, together with identification and inductive verification of their loop structures. We have evaluated our framework on transformations applied by an open source behavioral synthesis tool to designs from the CHStone benchmark. Our tool can automatically validate more than 75 percent of the total of 1008 compiler transformations applied, taking an average time of 1.5 seconds per transformation. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 454762 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479930173 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-06-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Optimization Explosions Benchmark testing Complexity theory Image edge detection Hardware Manuals |
| Content Type | Text |
| Resource Type | Article |
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