NDLI: On timing closure: Buffer insertion for hold-violation removal

Content Provider	IEEE Xplore Digital Library
Author	Pei-Ci Wu Wong, M.D.F. Nedelchev, I. Bhardwaj, S. Parkhe, V.
Copyright Year	2014
Description	Author affiliation: Mentor Graphics Corp., Fremont, CA, USA (Nedelchev, I.; Bhardwaj, S.; Parkhe, V.) \|\| Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Champaign, IL, USA (Pei-Ci Wu; Wong, M.D.F.)
Abstract	Timing closure, which is to meet the design's timing constraints, is a key problem in the physical design flow. During the timing optimization process, buffers can be used to speedup the circuit or serve as delay elements. In this paper, we study the hold-violation removal problem for today's industrial designs. Discrete buffers, accurate timing models/analysis, and complex timing constraints make the problem difficult and time-consuming to solve. In this paper, we first present a linear programming-based methodology to model the setup and hold-time constraints. Then based on the solution to the linear programming, buffers are inserted as delay elements to solve hold violations. In the experiment, our approach is tested on industrial designs, then runs with the industrial optimization flow, and better results in terms of hold violations and runtime are reported.
Starting Page	1
Ending Page	6
File Size	216183
Page Count	6
File Format	PDF
ISBN	9781479930173
DOI	10.1145/2593069.2593171
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delays Pins Linear programming Optimization Combinational circuits Integrated circuit modeling buffer insertion Timing optimization physical synthesis
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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