NDLI: A SystemC Virtual Prototyping based methodology for multi-standard SoC functional verification

Content Provider	IEEE Xplore Digital Library
Author	Zhimiao Chen Yifan Wang Lei Liao Ye Zhang Aytac, A. Muller, J.H. Wunderlich, R. Heinen, S.
Copyright Year	2014
Description	Author affiliation: Integrated Analog Circuits & RF Syst., Aachen, Germany (Zhimiao Chen; Yifan Wang; Lei Liao; Ye Zhang; Aytac, A.; Muller, J.H.; Wunderlich, R.; Heinen, S.)
Abstract	This paper describes a functional verification methodology for multi-standard wireless Systems-on-Chip (SoC) based on SystemC Virtual Prototyping (VP). The proposed semi-automatic pin-accurate RF VP generation method reduces huge handcrafting work to abstract circuitry into the event-driven simulation domain with satisfactory accuracy, while enabling the flexibility to choose different abstraction levels. A seamless transition between various signal abstractions is enabled by operator overload, e.g. passband and equivalent baseband in order to minimize simulation time according to test cases. This methodology is demonstrated for a low power RF transceiver with the achieved simulation speed of 500μs in 10s computation time.
Starting Page	1
Ending Page	6
File Size	582413
Page Count	6
File Format	PDF
ISBN	9781479930173
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Integrated circuit modeling Radio frequency System-on-chip Mathematical model Baseband Hardware design languages Accuracy
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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