NDLI: Containing timing-related certification cost in automotive systems deploying complex hardware

Content Provider	IEEE Xplore Digital Library
Author	Kosmidis, L. Quinones, E. Abella, J. Farrall, G. Wartel, F. Cazorla, F.J.
Copyright Year	2014
Description	Author affiliation: Infineon Technol., Bristol, UK (Farrall, G.) \|\| AIRBUS, France (Wartel, F.) \|\| Barcelona Supercomput. Center, Barcelona, Spain (Quinones, E.; Abella, J.; Cazorla, F.J.) \|\| Univ. Politec. de Catalunya, Barcelona, Spain (Kosmidis, L.)
Abstract	Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the timing behaviour of the hardware/software platform: execution times of end-to-end runs have to be independent and identically distributed (i.i.d.). Hardware and software solutions have been deployed to accomplish MBPTA requirements. The latter has achieved the i.i.d. properties running on some commercial off-the-shelf (COTS) processor designs. Unfortunately, software randomisation challenges functional verification needed for certification since it introduces indirections through pointers in the code. In this paper we propose a new approach to software randomisation able to contain its functional verification costs. Our approach performs software randomisation statically, as opposed to current dynamic approaches. We carefully review the requirements of the new approach and prove its feasibility.
Starting Page	1
Ending Page	6
File Size	555809
Page Count	6
File Format	PDF
ISBN	9781479930173
DOI	10.1145/2593069.2593112
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Software Timing Hardware Probabilistic logic Vehicle dynamics Standards Certification Real-time WCET
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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