NDLI: Datapath synthesis for overclocking: Online arithmetic for latency-accuracy trade-offs

Content Provider	IEEE Xplore Digital Library
Author	Kan Shi Boland, D. Stott, E. Bayliss, S. Constantinides, G.A.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK (Kan Shi; Boland, D.; Stott, E.; Bayliss, S.; Constantinides, G.A.)
Abstract	Digital circuits are currently designed to ensure timing closure. Releasing this constraint by allowing timing violations could lead to significant performance improvements, but conventional forms of computer arithmetic do not fail gracefully when pushed beyond deterministic operation. In this paper we take a fresh look at Online Arithmetic, originally proposed for digit serial operation, and synthesize unrolled digit parallel online operators to allow for graceful degradation. We quantify the impact of timing violation on key arithmetic primitives, and show that substantial performance benefits can be obtained in comparison to binary arithmetic. Since timing errors are caused by long carry chains, these result in errors in least significant digits with online arithmetic, causing less impact than conventional implementations. Using analytical models and empirical FPGA results from an image processing application, we demonstrate an error reduction over 89% and an improvement in SNR of over 20dB for the same clock rate.
Starting Page	1
Ending Page	6
File Size	1660053
Page Count	6
File Format	PDF
ISBN	9781479930173
DOI	10.1145/2593069.2593118
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delays Adders Field programmable gate arrays Clocks Standards Probabilistic logic Imprecise Design Online Arithmetic Overclocking
Content Type	Text
Resource Type	Article

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