NDLI: Low-power design of Reed-Solomon encoders

Content Provider	IEEE Xplore Digital Library
Author	Wei Zhang Jing Wang Xinmiao Zhang
Copyright Year	2013
Description	Author affiliation: Sch. of Electron. Inf. Eng., Tianjin Univ., Tianjin, China (Wei Zhang; Jing Wang) \|\| Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA (Xinmiao Zhang)
Abstract	Reed-Solomon (RS) codes are one of the most widely used block error-correcting codes in modern communication and computer systems. Multiplication is the key computation in RS encoding. Adopting the generator polynomial with symmetric coefficients, the number of multipliers in RS encoders can be reduced by half, and their power consumption may also reduce. However, in some cases, the encoder based on the generator polynomial with asymmetric coefficients have better power performance. Additionally, since more than one primitive polynomial can generate a finite field with certain order, different choices of primitive polynomial also change the complexity of multipliers. In this paper, we exploited the relationship between the power consumption of RS encoders and their different encoding parameters. A simple way to find the encoder with the lowest power consumption is also presented. Simulation results prove its effectiveness.
Starting Page	1560
Ending Page	1563
File Size	344918
Page Count	4
File Format	PDF
ISBN	9781467357609
ISSN	02714302
e-ISBN	9781467357623
DOI	10.1109/ISCAS.2013.6572157
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-19
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Polynomials Power demand Encoding Generators Complexity theory Logic gates Reed-Solomon codes
Content Type	Text
Resource Type	Article

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