NDLI: Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays

Content Provider	IEEE Xplore Digital Library
Author	Yuanbo Zhu Jigang Wu Siew-Kei Lam Srikanthan, T.
Copyright Year	2013
Description	Author affiliation: Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore, Singapore (Siew-Kei Lam; Srikanthan, T.) \|\| Sch. of Comput. Sci. & Software Eng., Tianjin Polytech. Univ., Tianjin, China (Yuanbo Zhu; Jigang Wu)
Abstract	This paper presents a heuristic approach to accelerate the reconfiguration of two-dimensional degradable VLSI arrays linked by 4-port switches in presence of faulty processing elements (PEs). In particular, we proposed a technique to preprocess the host array by 1) identifying fault-free PEs that cannot form the target array due to their proximity to faulty PEs, and 2) labeling these fault-free PEs as faults. The proposed preprocessing method minimizes the number of PEs that will be considered for reconfiguration, thus accelerating the reconfiguration process. Simulation results show that the runtime of two well-known algorithms are significantly reduced by employing the preprocessing technique. In addition, we demonstrate the scalability of the proposed technique by showing that the runtime reduction rate increases with increasing fault density.
Starting Page	2424
Ending Page	2427
File Size	491869
Page Count	4
File Format	PDF
ISBN	9781467357609
ISSN	02714302
e-ISBN	9781467357623
DOI	10.1109/ISCAS.2013.6572368
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-19
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Runtime Very large scale integration Algorithm design and analysis Arrays Fault diagnosis Fault tolerance Fault tolerant systems
Content Type	Text
Resource Type	Article

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