NDLI: An interface for the $I^{2}C$ protocol in the WaferBoard™

Content Provider	IEEE Xplore Digital Library
Author	Hussain, W. Savaria, Y. Blaquiere, Y.
Copyright Year	2013
Abstract	This paper presents a circuit proposed for the $DreamWafer^{TM}$ technology. This circuit can interconnect several pads, also called NanoPads, in such a way that they can imitate the behavior of a single metal line for open-drain (or open-collector) buses compliant to the $I^{2}C$ protocol. Thus, multiple serial data lines (SDA) and serial clock lines (SCL) from different user ICs can be connected together on the $Waferboard^{TM}.$ The interface can support up to 25 $I^{2}C$ IC pins together. It can support bidirectional data transfers at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed mode. The entire interface would take less than 1% of the total area of the $WaferIC^{TM},$ the target system environment for which this circuit is proposed.
Starting Page	1492
Ending Page	1495
File Size	332242
Page Count	4
File Format	PDF
ISBN	9781467357609
ISSN	02714302
e-ISBN	9781467357623
DOI	10.1109/ISCAS.2013.6572140
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-19
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols Logic gates MOS devices Integrated circuit interconnections Registers Standards Sensors Bidirectional Bus Re-programmable Circuit Board I²C protocol Open Collector Bus
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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