NDLI: An empirical approach for digital currency forensics

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2015 IEEE International Symposium on Circuits and Systems (ISCAS)

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

General chairs' message

Table of contents

Image search reranking with multi-latent topical graph

Context-dependent audio-visual and temporal features fusion for TV commercial detection

Quality perception in 3D interactive environments

A gradient-based approach for interference cancelation in systems with multiple Kinect cameras

Rate-Distortion Optimization for depth map coding with distortion estimation of synthesized view

Model and design considerations for multistage electrostatic microgenerators

A self-sustaining integrated CMOS regulator for solar and UHF RFID energy harvesting systems

Maximizing efficiency through impedance matching from a circuit-centric model of non-radiative resonant wireless power transfer

A reconfigurable micro power solar energy harvester for ultra-low power autonomous microsystems

Wide-range, reference free, on-chip voltage sensor for variable Vdd operations

Multi layer based rate control algorithm for HEVC

Early termination schemes for fast intra mode decision in High Efficiency Video Coding

HEVC-based adaptive quantization for screen content by detecting low contrast edge regions

Fast HEVC intra mode decision using matching edge detector and kernel density estimation alike histogram generation

View synthesis prediction using skip and merge candidates for HEVC-based 3D video coding

A cognitive radio receiver front-end IC based on spread spectrum sensing technique

DOA-estimation and source-localization in CR-networks using steerable 2-D IIR beam filters

Papoulis-Gerchberg Hybrid Filter Bank receiver for cognitive-/Software-Defined Radio systems

Variable increment step based reconfigurable interleaver for multimode communication application

A tunable inductance topology to realize frequency tunable matching networks and amplifiers

FIR filter with variable fractional delay and phase shift: Efficient realization and design using reweighted l1-norm minimization

Error spectrum shaping approach for lattice filter roundoff noise reduction

Design of two-dimensional notch filter using bandpass filter and fractional delay filter

Low-complexity general FIR filters based on Winograd's inner product algorithm

Sparse FIR filter design based on Genetic Algorithm

Trends on the application of emerging nonvolatile memory to processors and programmable devices

MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI

A comparative study of STT-MTJ based non-volatile flip-flops

MLC STT-RAM design considering probabilistic and asymmetric MTJ switching

Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor

Design of a low-power pulse-triggered flip-flop with conditional clock technique

A 32.4 μW RF front end for 2.4 GHz wake-up receiver

A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs

Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection

Ultra-low-power high sensitivity spike detectors based on modified nonlinear energy operator

A current-mode flash ADC for low-power continuous-time sigma delta modulators

A current mode 6-bit self-clocked tracking ADC with adaptive clock frequency for DC-DC converters

A frequency-folded ADC architecture with digital LO synthesis

A merged first and second stage for low power pipelined ADC

High-order multi-bit incremental converter with Smart-DEM algorithm

A configurable multi-band GNSS receiver for Compass/GPS/Galileo applications

A spur cancellation technique for MDLL-based frequency synthesizers

A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing

Minimum-jitter design of bang-bang PLLs in the presence of $1/f^{2}$ and $1/f^{3}$ DCO noise

Phase-locked loop based PWM wireless transmitter

A highly linear, Sigma-Delta based, sub-Hz high-pass filtered ExG readout system

REFET replication for ISFET-based SNP detection arrays

A direct-capacitive feedback ISFET interface for pH reaction monitoring

A floating active inductor based CMOS cochlea filter with high tunability and sharp cut-off

PLL-based high-speed demodulation of FM signals for real-time AFM applications

Some fingerprints of ideal memristors

PSpice switch-based versatile memristor model

Composite memristance of parallel and serial memristor circuits

Unified modeling for memristive devices based on charge-flux constitutive relationships

Physics-based memristor models

A joint reconstruction algorithm for multi-view compressed imaging

Content based fast prediction unit quadtree depth decision algorithm for HEVC

Partial encryption by randomized zig-zag scanning for video encoding

A parallel deblocking filter based on H.264/AVC video coding standard

Rate-distortion optimized block classification and bit allocation in screen video compression

A hybrid MPPT method for Photovoltaic systems via estimation and revision method

Low-cost global MPPT scheme for Photovoltaic systems under partially shaded conditions

Distributed control of reactive power from photovoltaic inverters

Battery-assisted and photovoltaic-sourced switched-inductor CMOS harvesting charger-supply

Low-complexity feedback-channel-free distributed video coding with enhanced classifier

Multiple description coding with randomly offset quantizers

Improved hierarchial intra prediction based on adaptive interpolation filtering for lossless compression

Region-based weighted prediction algorithm for H.264/AVC video coding

Content-aware write reduction mechanism of phase-change RAM based Frame Store in H.264 Video codec system

Performance of a multiple-access DCSK-CC system over Nakagami-m fading channels

Forward error correction with RaptorQ code on GPU

Design and implementation of an ML decoder for tail-biting convolutional codes

Fully integrated passive UHF RFID transponder IC with a sensitivity of −12 dBm

Hardware acceleration of the robust header compression (RoHC) algorithm

A detection method of nasalised vowels based on an acoustic parameter derived from phase spectrum

Improved structural similarity measurement for vocal signals

Auditory features based on Gammatone filters for robust speech recognition

Evaluation of detailed modeling of the LP residual in statistical speech synthesis

Potential and pitfalls of silicon photonics computing and interconnect

System-level analysis of mesh-based hybrid optical-electronic network-on-chip

MHYNESYS II: Multi-stage hybrid Network on chip synthesis for Next Generation 3D IC Manycore

Recent advances in optical Reservoir Computing

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction

Low complexity image rejection demodulator for bluetooth LE applications

Power optimization in a parallel multiplier using voltage islands

A low power register file with asynchronously controlled read-isolation and software-directed write-discarding

Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU

Mitigating timing errors in time-interleaved ADCs: A signal conditioning approach

10b 150MS/s $0.4mm^{2}$ 45nm CMOS ADC based on process-insensitive amplifiers

A 5-bit 1.5GSps calibration-less binary search ADC using threshold reconfigurable comparators

Rigorous analysis of quantization error of an A/D converter based on β-map

A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW

Linearization of subthreshold low-noise amplifiers

Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers

1V rail-to-rail constant Gm amplifier with common-mode elimination technique

An inductorless wideband low noise amplifier with current reuse and linearity enhancement

A current-mirror opamp with switchable transconductances for low-power switched-capacitor integrators

A multi-channel multi-mode physiological signals acquisition and analysis platform

A bidirectional neural interface with a HV stimulator and a LV neural amplifier

A 1.83 μW, 0.78 μVrms input referred noise neural recording front end

A current-mode stimulator circuit with two-step charge balancing background calibration

A VLSI design of singular value decomposition processor used in real-time ICA computation for multi-channel EEG system

Memristor-based neural circuits

Features of memristor emulator-based artificial neural synapses

Temporal processing with volatile memristors

Analysis of multi-memristor circuits

A fast rate adaptation scheme for SVC based on the packet dependencies

Lifetime elongation of event-driven wireless video sensor networks

Adaptive mode and modulation coding switching scheme in MIMO multicasting system

A collusion-free key assignment scheme for hierarchical access control using recursive hash chains

Optimal resource allocation for multimedia application providers in multi-site cloud

Identifying groups of preventive controls for a set of critical contingencies in the context of voltage stability

Practical stability assessement of distributed synchronous generators under load variations

Saddle-node bifurcation in three-phase unbalanced distribution networks with distributed generators

BCS: A Binary Cuckoo Search algorithm for feature selection

A set of independent admittance bases for decoupled analysis of unbalanced three-phase systems

Acceleration of rate-distortion optimized quantization for H.264/AVC

QP refinement according to Lagrange multiplier for High Efficiency Video Coding

Rate-distortion optimization with adaptive weighted distortion in high Efficiency Video Coding

Low-complexity content-adaptive Lagrange multiplier decision for SSIM-based RD-optimized video coding

Perceptual rate distortion optimization for block mode selection in hybrid video coding

Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder

CMOS receiver with equalizer and CDR for short-reach optical communications

A highly-efficient multi-band multi-mode digital quadrature transmitter with 2D pre-distortion

A high throughput ASIC design for IPv6 routing lookup system

A 5.8GHz integrated CMOS transmitter for Chinese electronic toll collection system

Thresholding-based online algorithms of complexity comparable to sparse LMS methods

New constrained affine-projection adaptive-filtering algorithm

New proportionate affine projection sign algorithms

Special properties of the modified DFT to achieve algorithmic fault tolerance in Adaptive Filters

Acoustic feedback neutralization in digital hearing aids — A two adaptive filters-based solution

Cyber-physical management for heterogeneously integrated 3D thousand-core on-chip microprocessor

3D stacking for multi-core architectures: From WIDEIO to distributed caches

Impact of manufacturing process variations on performance and thermal characteristics of 3D ICs: Emerging challenges and new solutions

Exploring early design tradeoffs in 3DIC

An inductive-coupling interconnected application-specific 3D NoC design

FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?

A process-variation compensation scheme to operate CMOS digital logic cells in deep sub-threshold region at 80mV

Ultra low power NEMFET based logic

Minimum energy point tracking for sub-threshold digital CMOS circuits using an in-situ energy sensor

A DAC cell with improved ISI and noise performance using native switching for multi-bit CT Delta Sigma modulators

Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators

Background adaptive linearization of high-speed digital-to-analog Converters

A low power 1-MHz continuous-time ΣΔM Using a passive loop filter designed with a genetic algorithm tool

A distortion corrected passive RC noise shaping ADC for biomedical applications

A switched gain cell parametric amplifier

A design methodology to achieve low input impedance and non-constant gain-bandwidth product in TIAs for optical communication

A 94% efficiency near-constant frequency self-oscillating class-D audio amplifier with voltage control resistor

A fully differential CMOS self-biased two-stage preamplifier-latch threshold detection comparator

RF current mode class-D power amplifiers under periodic and non-periodic switching conditions

Control methodology for on-chip switching power supplies for biomedical implants

A 2-MHZ, process and voltage compensated clock oscillator for biomedical implantable SoC in 0.18-μm CMOS

A 281-nW 43.3 fJ/conversion-step 8-ENOB 25-kS/s asynchronous SAR ADC in 65nm CMOS for biomedical applications

A low power BPSK demodulator for wireless implantable biomedical devices

Wireless Power Transfer H-Bridge design with serial resonance and varying supply voltage

Challenges in circuits for visual prostheses

A multi-channel neural stimulator with resonance compensated inductive receiver and closed-loop smart power management

A CMOS microchip-based retinal prosthetic device for large numbers of stimulation in wide area

Capacitive-data links, energy-efficient and high-voltage compliant visual intracortical microstimulation system

Quality control of real-time panoramic views from the smart camera 360SCAN

TURNUS: A design exploration framework for dataflow system design

A low-cost scalable Voltage-Frequency Adjustor for implementing low-power systems

Live demonstration: Real-time audio restoration using sparse signal recovery

Live demonstration: High level software and hardware synthesis of dataflow programs

Live demonstration: Axon emulator for evaluation of nerve recording systems

Unipolar ECG circuits: Towards more precise cardiac event identification

Live demonstration: Multiple-timescale plasticity in a neuromorphic system

Live demonstration: A high-speed-pass asynchronous motion detection sensor

Live demonstration: A wireless force measurement system for total knee arthroplasty

A high-throughput VLSI architecture for deblocking filter in HEVC

Fully pipelined DCT/IDCT/Hadamard unified transform architecture for HEVC Codec

A custom GZIP decoder for DTV application

Memory-efficient scalable video encoder architecture for multi-source digital home environment

A 34.1fps scale-space processor with two-dimensional cache for real-time object recognition

High-side NMOS power switch and bootstrap driver for high-frequency fully-integrated converters with enhanced efficiency

Analysis and design of three-state controlled transition mode for a buck-boost converter with efficiency and stability enhancement

A series of exponential step-down switched-capacitor converters and their applications in two-stage converters

Design of reliable 2×VDD and 3×VDD series-parallel charge pumps in nanoscale CMOS

A fully integrated switched-capacitor based PMU with adaptive energy harvesting technique for ultra-low power sensing applications

A new multi-view articulated human motion tracking algorithm with improved silhouette extraction and view adaptive fusion

Object segmentation from wide baseline video

LSGP: Line-SIFT Geometric Pattern for wide-baseline image matching

A new finger touch detection algorithm and prototype system architecture for pervasive bare-hand human computer interaction

Image enhancement for fringe projection profilometry

A 65nm CMOS wide-band LNA with continuously tunable gain from 0dB to 24dB

Low power, high linearity multi-mode downconversion mixer for SDR

Multi-band wide tuning range CMOS VCO with Hybrid Inductor for LTE standard

An adaptive class-E power amplifier with improvement in efficiency, reliability and process variation tolerance

SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter

Single underwater image enhancement with a new optical model

Image enlargement using the giga-vision sensor model

Fuzzy logic and additive wavelet based image fusion

Hybrid image interpolation with soft-decision kernel regression

Scan-controlled pulse flip-flops for mobile application processors

Efficient in situ error detection enabling diverse path coverage

Implementation of hybrid version management in hardware transactional memory

Redefining the relationship between scalar and parallel units in SIMD architectures

Collaborative error control method for sequential logic circuits

Logic-on-logic partitioning techniques for 3-dimensional integrated circuits

A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c

An efficient VLSI architecture of QPP interleaver/deinterleaver for LTE turbo coding

Microchannel splitting and scaling for thermal balancing of liquid-cooled 3DIC

Modelling NEM relays for digital circuit applications

A voltage scaling 0.25–1.8 V delta-sigma modulator with inverter-opamp self-configuring amplifier

A 1-V 100-dB dynamic range 24.4-kHz bandwidth delta-sigma modulator

A low-power, ultra low-offset, 16.5-bit, ΣΔ ADC for coulomb counting and fuel gauge applications

Design of a third-order ΣΔ modulator with minimum op-amps output swing

An empirical and statistical comparison of state-of-the-art sigma-delta modulators

Mathematical analysis of inter-band intermodulation for concurrent dual-band mixers

Nonlinearity analysis of R-2R ladder-based current-steering digital to analog converter

A fully integrated video digital-to-analog converter with minimized gain error

Two-stage charge sensitive amplifier with self-biased MOS transistor as continuous reset system

A SiGe 8-channel comparator for application in a synthetic aperture radiometer

A 1.52 uJ/classification patient-specific seizure classification processor using Linear SVM

Similarity-index early seizure detector VLSI architecture

Low-power multi-processor system architecture design for universal biomedical signal processing

Reconfigurable biological signal co-processor for feature extraction dedicated to implantable biomedical microsystems

System level model for transcutaneous optical telemetric link

Mobile media communication, processing, and analysis: A review of recent advances

Effective retargeting for image coding

Inter-screen interaction for session recognition and transfer based on cloud centric media network

Mobile multimedia travelogue generation by exploring geo-locations and image tags

Compact descriptors for mobile visual search and MPEG CDVS standardization

Efficient loop accelerator for Motion Estimation Specific Instruction-set Processor

Hardware implementation for real-time 3D rendering in 2D-to-3D conversion

Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor

DRAM access reduction in GPUs by thread-block scheduling for overlapped data reuse

Salient object cutout using Google images

94% Performance improvement by time-shift control (TSC) technique in cloud computing voltage regulator module (VRM)

Effect of MOSFET parasitic capacitances on EER transmitter with class-E amplifier

High-PF and ultra-low-THD power factor correction controller by sinusoidal-wave synthesis and optimized THD control

Switching and conduction loss analysis of buck converters operating in DCM-only scenarios

Bifurcation analysis in dual-input buck converter in hybrid power system

Data-driven human motion synthesis based on angular momentum analysis

Visual masking estimation based on structural uncertainty

Separation of weak reflection from a single superimposed image using gradient profile sharpness

A visual attention model for news video

Saliency detection using a central stimuli sensitivity based model

An energy efficient antenna selection for large scale green MIMO systems

A digital centric transmitter architecture with arbitrary ratio baseband-to-LO upsampling

Reconfigurable feeding network for GSM/GPS/3G/WiFi and global LTE applications

A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication in 65nm CMOS

Design of self-biased fully differential receiver and crosstalk cancellation for capacitive coupled vertical interconnects in 3DICs

A novel region merging based image segmentation approach for automatic object extraction

HTS: A new shape descriptor based on Hough Transform

Gradient Local Binary Patterns for human detection

Segmenting specific object based on logo detection

A novel implementation scheme for high area-efficient DCT based on signed stochastic computation

Optimization of ETSI DSR frontend software on a high-efficient audio DSP

A high-throughput low-latency arithmetic encoder design for HDTV

A 32.8mW 60fps cortical vision processor for spatio-temporal action recognition

A reconfigurable inverse transform architecture design for HEVC decoder

Cluster-based distributed active current timer for hardware Trojan detection

Robust random chip ID generation with wide-aperture clocked comparators and maximum likelihood detection

A power-efficient scan tree design by exploring the Q'-D connection

Development of hybrid electrical model for CNT based Through Silicon Vias

Concurrent estimation of amplifier nonidealities and excess loop delay in continuous-time sigma-delta modulators

Direct delta-sigma receiver: Analysis, modelization and simulation

A 1.7mW quadrature bandpass ΔΣ ADC with 1MHz BW and 60dB DR at 1MHz IF

A multi-stage and time-based continuous time ΣΔ Architecture using a Gated Ring Oscillator

Approaches to the implementation of noise-coupling in continuous-time Delta-Sigma modulators

Analog signal processing solutions for particle physics detectors: Upgrade of the LHCb calorimeter electronics

A compact analog active time delay line using SiGe BiCMOS technology

Design and analysis of full-chip HV ESD protection in BCD30V for mixed-signal ICs

Reliability degradation with electrical, thermal and thermal gradient stress in interconnects

A simple analog CMOS design tool using transistor dimension-independent parameters

A portable lab-on-chip platform for magnetic beads density measuring

Characterization of standard CMOS compatible photodiodes and pixels for Lab-on-Chip devices

Human respiratory feature extraction on an UWB radar signal processing platform

Efficient implementation of real-time ECG derived respiration system using cubic spline interpolation

A low power low inaccuracy linearity-compensated temperature sensor for attachable medical devices

Overview of quality assessment for visual signals and newly emerged trends

A new reduced-reference image quality assessment using structural degradation model

Paired comparison for subjective multimedia quality assessment: Theory and practice

Adaptive contrast adjustment for postprocessing of tone mapped high dynamic range images

On the impact of packet-loss impairments on visual attention mechanisms

A transformer neutralization based 60GHz LNA in 65 nm LP CMOS with 22dB gain and 5.5dB NF

12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS

A 12–40 GHz low phase variation highly linear BiCMOS variable gain amplifier

A 3.4dB NF k-band LNA in 65nm CMOS technology

Inductorless, powerl-proportional, optical receiver front-end in TSMC 90 nm

A new, delay-line-discriminator-based, hybrid RF/digital phase noise cancellation technique

Multi-carrier LINC amplifier calibration by min-minimum criterion

Improving the error correction capability of arithmetic coding by forecasting forbidden symbols

Novel adaptive soft input soft output demodulator for serially concatenated CPM signals

Blind identifiability of general constellations

Channel estimation for MIMO-OFDM systems based on Subspace Pursuit algorithm

Adaptive channel scheduling for Scalable Video broadcasting over MIMO wireless networks

Performance analysis of transform in uncoded wireless visual communication

Hybrid digital-analog scheme for video transmission over wireless

Adaptive packet encapsulation of Scalable Video Coding bitstream

A 10-bit fast lock all-digital data recovery with CR oscillator reference for automotive network

Analysis of a class of decimated clock/data recovery architectures for serial links

A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation

A 0.7pJ/bit 2Gbps self-synchronous serial link receiver using gated-ring oscillator for inductive coupling communication

A fully-differential adaptive equalizer using the spectrum-balancing technique

Fast single frame super-resolution using scale-invariant self-similarity

Spatially-varying super-resolution for HDTV

Robust super-resolution for face images via principle component sparse representation and least squares regression

Illumination-invariance and nonlocal means based super resolution

Improving dictionary based image super-resolution with nonlocal total variation regularization

Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs

FPGA implementation of a scheduler supporting parallel dataflow execution

Parallelization techniques for implementing trellis algorithms on graphics processors

CASL hypervisor and its virtualization platform

Network partitioning and GA heuristic crossover for NoC application mapping

Power-aware buddy system and task group scheduler

Low-energy and low-latency error-correction for phase change memory

Using condition flag prediction to improve the performance of out-of-order processors

Designing scratchpad memory architecture with emerging STT-RAM memory technologies

An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications

Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface

Hybrid incremental-ΣΔ-ADC for ambient light sensing applications

Power and area efficient comb-based decimator for Sigma-Delta ADCs with high decimation factors

Calculating transfer functions of CT sigma-delta modulators with arbitrary DAC waveforms

Analysis and design of high speed/high linearity continuous time delta-sigma modulator

A type of lumped-element-based analog filters based on transversal circuit networks

A Steerable DC-1 GHz all-pass filter-Sum RF space-time 2-D beam filter in 65 nm CMOS

A 54dB-DR 1-GHz-bandwidth continuous-time low-pass filter with in-band noise reduction

An inductorless 3–5 GHz band-pass filter with tunable center frequency in 90 nm CMOS

Improved technique for continuous tuning of CMOS transconductor

Error correction algorithm for high accuracy bio-impedance measurement in wearable healthcare applications

An efficient DCT-IV-based ECG compression algorithm and its hardware accelerator design

Wireless wearable ECG sensor design based on level-crossing sampling and linear interpolation

Influence of prior knowledge on the accuracy limit of parameter estimation in single-molecule fluorescence microscopy

Identification of motor neuron disease using wavelet domain features extracted from EMG signal

Extracting underlying trend and predicting power usage via joint SSA and sparse binary programming

Steady state reliability of maximum power point tracking algorithms used with a thermoelectric generator

A generalized droop-control scheme for decentralized control of inverter-interfaced microgrids

Stability issues in cascade connected switching converters for DC microgrid applications

A isolated bidirectional interleaved flyback converter for battery backup system application

Low-complexity finite alphabet iterative decoders for LDPC codes

Memory efficient EMS decoding for non-binary LDPC codes

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

High-performance iterative BCH decoder architecture for 100 Gb/s optical communications

Low-complexity layered iterative hard-reliability-based majority-logic decoder for non-binary quasi-cyclic LDPC codes

A new algorithm for compressive sensing based on total-variation norm

A two-class information concealing system based on compressed sensing

A rakeness-based design flow for Analog-to-Information conversion by Compressive Sensing

Gating and robust EKF based target tracking in mixed LOS/NLOS environments

Compressive sensing recovery from non-ideally quantized measurements

A hardware CABAC encoder for HEVC

Flexible integer DCT architectures for HEVC

An FPGA co-processor for adaptive lane departure warning system

Buffer optimization based on critical path analysis of a dataflow program design

A new bandwidth adaptive non-local kernel regression algorithm for image/video restoration and its GPU realization

A 7 mW 2.5 GHz spread spectrum clock generator using switch-controlled injection-locked oscillator

A 40Gb/s 860μW single-phase 4:1 multiplexer in 45nm CMOS

A self-calibrating multi-VCO PLL scheme with leakage and capacitive modulation mitigations

A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology

SSC tracking analysis and a deeper-SSC estimator

Video compression using 3D multiscale recurrent patterns

Effective early termination using adaptive search order for frame rate up-conversion

Stereo matching by adaptive weighting selection based cost aggregation

Line-based distributed coding scheme for onboard lossless compression of high-resolution stereo images

Personal photo album compression and management

Concurrent faulty clock detection for crypto circuits against clock glitch based DFA

A high-performance low-power SoC for mobile one-time password applications

High-efficient hardware design based on enhanced Tschirnhaus transform for solving the LSPs

PCKGen: A Phase Change Memory based cryptographic key generator

39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI

An improved read/write scheme for anchorless NEMS-CMOS non-volatile memory

CMOS SRAM scaling limits under optimum stability constraints

0.18 μm CMOS process photodiode memory

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

An auto-reconfigurable dual-output SC DC-DC regulator with sub-harmonic fixed on-time control for energy-harvesting applications

An all-subthreshold, 0.75V supply, 2ppm/°C, CMOS Voltage Reference

A low voltage low output impedance CMOS bandgap voltage reference

Output-capacitorless CMOS LDO regulator based on high slew-rate current-mode transconductance amplifier

A FVF based output capacitorless LDO regulator with wide load capacitance range

An interface for the $I^{2}C$ protocol in the WaferBoard™

A radiation-hardened DLL with fine resolution and DCC for DDR2 memory interface in 0.13 μm CMOS

A $0.3mm^{2}$ 60μW 11.2b ENOB signal acquisition ASIC for resistive bridge sensors

A 5-V 555-μW 0.8-μm CMOS MEMS capacitive sensor interface using correlated level shifting

A low-power ratiometric single/differential quasi-digital converter

High effective medical image segmentation with model adjustable method

Lobe asymmetry-based automatic classification of brain magnetic resonance images

Reconstruction of neural action potentials using signal dependent sparse representations

Estimation of time-varying autocorrelation and its application to time-frequency analysis of nonstationary signals

Real-time assessment of vigilance level using an innovative Mindo4 wireless EEG system

Convergence regions of Newton method in power flow studies: Numerical studies

Homotopy-enhanced power flow methods for general distribution networks with distributed generators

Probabilistic load margins of power systems embedded with wind farms

Modeling and simulation of information-embedded multi-converter power systems

Towards development of a CUEP method for Network-preserving power system models

Optimized algorithms for binary BCH codes

Two programmable BCH soft decoders for high rate codes with large word length

Low-power design of Reed-Solomon encoders

Analog and digital approaches for an energy efficient low complexity channel decoder

Dependability-increasing technique for a multi-context optically reconfigurable gate array

System analysis and energy model for radio-triggered battery-less monolithic wireless sensor receiver

A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL

Improved lifetime routing for Wireless Sensor Networks

A super-regenerative pulsed UWB receiver combined with injection-locking

A UWB mixer with a balanced wide band active balun using crossing centertaped inductor

An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity

Stochastic resonance in an analog current-mode neuromorphic circuit

A floating-gate analog memory with bidirectional sigmoid updates in a standard digital process

Genetic Algorithm with virus infection for finding approximate solution

A multi-modal and tunable Radial-Basis-Funtion circuit with supply and temperature compensation

Analog implementation of encoded neural networks

Excitatory and Inhibitory Memristive Synapses for Spiking Neural Networks

A spiking-neuron collective analog adder with scalable precision

Spike-based analog-digital neuromorphic information processing system for sensor applications

Application of neural networks with CSD coefficients for human face recognition

Disparity vector based advanced inter-view prediction in 3D-HEVC

Inter-layer intra mode coding for the scalable extension of HEVC

Fast zero block detection and early CU termination for HEVC Video Coding

Directional block compressed sensing for image coding

A mode-mapping and optimized MV conjunction based MGS-scalable SVC to AVC IPPP transcoder

Time-Division-Multiplexer based routing algorithm for NoC system

Implementation and optimization of 3780-point FFT on multi-core system

Traffic- and Thermal-aware Adaptive Beltway Routing for three dimensional Network-on-Chip systems

A run-time adaptive multiprocessor system

High-performance multiplierless transform architecture for HEVC

TSV-based on-chip inductive coupling communications

Differential pair sense amplifier for a robust reading scheme for memristor-based memories

Muller C-element based Decoder (MCD): A decoder against transient faults

Design and verification of an all-digital on-chip process variation sensor

A decoding algorithm with reduced complexity for non-binary LDPC codes over large fields

A meminductive circuit based on floating memristive emulator

New implementation of time domain measurement of quality factor

A LUT-free DC offset calibration method for removing the PGA-gain-correlated offset residue

A monolithic CMOS automatic biasing system for 40GHz multistage HEMT

An analytical model of the overshooting effect for multiple-input gates in nanometer technologies

A rapid analog amendment framework using the incremental floorplanning technique

Post-layout redundant wire insertion for fixing min-delay violations

Feasible transition path generation for EFSM-based system testing

Rules maps for scheduling algorithm knowledge

Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis

A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

Automatic verification of transition systems with unspecified components

Mobility overlap-removal based leakage power aware scheduling in high-level synthesis

Efficient middleware for network evaluation and optimization in Wireless Sensor Network design

An efficient method to compute phase-noise in injection-locked frequency dividers

A 47μW 204MHz AlN Contour-Mode MEMS based tunable oscillator in 65nm CMOS

Bang-bang phase detector model revisited

A mismatch-robust period-based VCO frequency comparison technique for ULP receivers

Simulating the synchronization of multi-scroll chaotic oscillators

On oscillatory dynamics of small-RNAs-mediated two-gene regulatory networks

Frustrated synchronization in two coupled polygonal oscillatory networks

Ultra-low-power 2.4 GHz Colpitts oscillator based on double feedback technique

A multilevel fingerprinting method for FPGA IP protection

A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration

A fast CAM-based image matching system on FPGA

A high speed configurable FPGA architecture for k-mean clustering

Compressed sensing SAR moving target imaging in the presence of basis mismatch

Sigma delta feedback DAC architectures for high accuracy and extremely low charge transfer

An ultra-low-power voltage-mode asynchronous WTA-LTA circuit

A low-power wide-dynamic-range readout IC for breath analyzer system

Link and energy adaptive UWB-based embedded sensing with renewable energy

Slew-rate enhancement for a single-ended low-power two-stage amplifier

A $0.3mm^{2}$ 10-b 100MS/s pipelined ADC using Nauta structure op-amps in 180nm CMOS

A switched-capacitor biquad using a simple quasi-unity gain amplifier

A multi-mode complex bandpass filter with gm-assisted power optimization and I/Q calibration

A low-noise amplifier with continuously-tuned input matching frequency and output resonance frequency

An LNA with optimally mismatched antenna interface for energy harvesting sensor nodes

Energy detection technique for ultra-low power high sensitivity wake-up receiver

Ring-VCO based low noise and low spur frequency synthesizer

Time domain probe insertion to find steady state of strongly nonlinear high-Q oscillators

A reconfigurable architecture for real-time prediction of neural activity

A 16-channel neural stimulator with DAC sharing scheme for visual prostheses

A switched-mode multichannel neural stimulator with a minimum number of external components

Design of an implantable stimulator ASIC with self-adapting supply

A flexible biphasic pulse generating and accurate charge balancing stimulator with a 1μW neural recording amplifier

A novel hardware implementation for joint heart rate, respiration rate, and gait analysis applied to body area networks

VLSI implementation of real-time motion compensated beamforming in synthetic transmit aperture imaging

A study of the partitioned dynamic programming algorithm for genome comparison in FPGA

An updated Cardiovascular Simulation Toolbox

Digital microfluidic system: A new design for heterogeneous sample based integration of multiple DMFBs

A remotely powered multi frequency RFID sensing tag with integrated impedance measurement interface

Micro-watt inductorless gm-boost LNA for biomedical implants

A variable bandwidth amplifier for a dual-mode low-power ΔΣ modulator in cardiac pacemaker system

A 1.5 μW NEO-based spike detector with adaptive-threshold for calibration-free multichannel neural interfaces

A low-power noise scalable instrumentation amplifier for fetal monitoring applications

Low-effort high-performance viterbi-based receiver for Bluetooth LE applications

Low-power programmable charge-domain sampler with embedded N-path bandpass filter for software-defined radio

Log-likelihood ratio algorithm for rate compatible modulation

A novel method to design wideband power amplifier for wireless communication

New blind multiuser detection DS-CDMA algorithm using simplified fourth order cumulant matrices

A 100Gb/s quad-rate transformer-coupled injection-locking CDR circuit in 65nm CMOS

Electromagnetic analysis on ring oscillator-based true random number generators

An improved push-pull driver using 0.13μm CMOS

Low complexity LFSR based bit-serial montgomery multiplier in $GF(2^{m})$

Compressive modulation in digital communication

Experimental results on wideband spectrum sensing using random sampling ADC in 90nm CMOS

A high resolution and high accuracy R-2R DAC based on ordered element matching

A novel energy-efficient serializer design method for gigascale systems

A low-power 0.5V regulator with settling enhancement for wireless sensor nodes

A 1.2V 10-bit 5 MS/s CMOS cyclic ADC

Low power quantizer design in CT Delta Sigma modulators

Undersampling RF-to-digital CT ΣΔ modulator with tunable notch frequency and simplified raised-cosine FIR feedback DAC

A 1.96-mW, 2.6-MHz bandwidth discrete time quadrature band-pass ΣΔ modulator

A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique

A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM

A 0.5-V 250-nW 65-dB SNDR passive ΔΣ modulator for medical implant devices

A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs

A 5-bit 1.25GS/s 4.7mW delay-based pipelined ADC in 65nm CMOS

Analysis and design of high performance frequency-interleaved ADC

Integrator swing reduction in feedback compensated Sigma-Delta modulators

A 0.5V rate-resolution scalable SAR ADC with 63.7dB SFDR

A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS

A 15-bit two-step sigma-delta ADC with embedded compression for image sensor array

A 1.5-bit/stage pipeline ADC with FFT-based calibration method

A Low power 10bit 500kS/s delta-modulated SAR ADC (DMSAR ADC) for implantable medical devices

A novel FIR filter based on stochastic logic

Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs

Reconfigurable FIR filter using distributed arithmetic on FPGAs

A VLSI DBSCAN processor composed as an array of micro agents having self-growing interconnects

A reconfigurable FFT architecture for variable-length and multi-streaming OFDM standards

Hardware-fault attack handling in RNS-based Montgomery multipliers

A floating gate graphene FET complementary inverter with symmetrical transfer characteristics

Power analysis attack of QCA circuits: A case study of the Serpent cipher

A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology

A monitoring circuit for NBTI degradation at 65nm technology node

3.5-D integration: A case study

A forward step for adaptive synchronization in directed complex networks

Convergence analysis of continuous-time systems based on feedforward neural networks

Stability analysis of multiple equilibria for recurrent neural networks with time-varying delays

Hybrid modelling of the general middle-sized genetic regulatory networks

Multi-Layer Perceptron including glial pulse and switching between learning and non-learning

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs

Low-power and compact NP dynamic CMOS adder with 16nm carbon nanotube transistors

CNTFET 8T SRAM cell performance with near-threshold power supply scaling

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET

A two-stage low complexity face recognition system for face images with alignment errors

A highly effective error concealment method for whole frame loss

Rain removal from dynamic scene based on motion segmentation

Adaptive general scale interpolation based on similar pixels weighting

Underwater optical image dehazing using guided trigonometric bilateral filtering

High-throughput hardware-efficient soft-input soft-output MIMO detector for iterative receivers

Approximate matrix inversion for high-throughput data detection in the large-scale MIMO uplink

Multidimensional Householder based high-speed QR decomposition architecture for MIMO receivers

Low-complexity decision directed method for carrier frequency offset estimation of IEEE 802.11ad

VLSI implementation of a low complexity 4×4 MIMO sphere decoder with table enumeration

Harmonic signal recovery and order estimation based on cascaded sparse processing

A precedence effect based far-field DoA estimation algorithm

An approach for joint blind space-time equalization and DOA estimation

Sparse linear arrays for estimating and tracking DOAs of signals with known waveforms

A low-power area-efficient compressive sensing approach for multi-channel neural recording

Noise model of indirect-feedback sigma-delta image sensors

Low-noise readout IC with integrated analog-to-digital conversion for radiation detection system

Scavenging thermal-noise energy for implementing long-term self-powered CMOS timers

A compressive piezoelectric front-end circuit for self-powered mechanical impact detectors

A signed integer programmable power-of-two scaler for ${2^{n}-1, 2^{n}, 2^{n}+1}$ RNS

An ultra-fast parallel architecture using sequential circuits computing on random bits

Non-iterative high speed division computation based on Mitchell logarithmic method

Delay-variation-tolerant FIR filter architectures based on the Residue Number System

High performance 3D-FFT implementation

The swapping binary-window DAC switching technique for SAR ADCs

A single SAR ADC converting multi-channel sparse signals

A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS

A SAR ADC with energy-efficient DAC and tri-level switching scheme

Analysis of back-end flash in a 1.5b/stage pipelined ADC

Digitally controlled wide range pulse width modulator for on-chip power supplies

How to reach 100% coding efficiency in multilevel burst-mode RF transmitters

Accurate time domain extraction of supercapacitor fractional-order model parameters

Coding efficiency of bandlimited PWM based burst-mode RF transmitters

A broadband Variable Gain Amplifier for the Square Kilometer Array

A 890fJ/bit UWB transmitter for SOC integration in high bit-rate transcutaneous bio-implants

A statistical MAC protocol for heterogeneous-traffic human body communication

An efficiency-enhanced wireless power transfer system with segmented transmitting coils for endoscopic capsule

An ultra-low-power monitoring system for inductively coupled biomedical implants

A Low-power wireless multi-channel surface EMG sensor with simplified ADPCM data compression

Theory and applications of complex networks: Advances and challenges

An adaptive routing algorithm for load balancing in communication networks

On the clustering coefficients of temporal networks and epidemic dynamics

Social learning with bounded confidence and probabilistic neighbors

New spectral graph theoretic conditions for synchronization in directed complex networks

Towards reliable hybrid bio-silicon integration using novel adaptive control system

Image processing by three-layer cellular neural networks with a new layer arrangement

Bifurcation analysis of delayed bidirectional associative memory neural networks

A model based comparison of BiFeO3 device applicability in neuromorphic hardware

Voting base online sequential extreme learning machine for multi-class classification

Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability

Design of nanosensing platform based on zinc oxide nanowire arrays

SRAM device and cell co-design considerations in a 14nm SOI FinFET technology

Statistical Electromigration analysis of a chip with the consideration of a within-die temperature map

Digital forensics for printed source identification

Region incrementing visual secret sharing scheme based on random grids

Optimized learning rate for energy waste minimization in a background subtraction based surveillance system

Depth map enhancement based on Z-displacement of objects

Self-adaptive scale transform for IQA metric

A 0.4V ultra low-power UWB CMOS LNA employing noise cancellation

An ultra-wideband receiving antenna array

A high gain ultra-wideband low noise amplifier with 802.11a interference rejection

A 3–5 GHz IR-UWB receiver front-end for wireless sensor networks

Video object detection by model-based tracking

Ground penetrating radar image enhancement using singular value decomposition

A multiple-candidate-regeneration-based object tracking system with enhanced learning capability by nearest neighbor classifier

Vehicle tracking iterative by Kalman-based constrained multiple-kernel and 3-D model-based localization

Multiple fish tracking via Viterbi data association for low-frame-rate underwater camera systems

Flame monitoring with an AER color vision sensor

2D motion sensor with programmable feature extraction

A 120μW 240×110@25fps vision chip with ROI detection SIMD processing unit

A low power multi-mode CMOS image sensor with integrated on-chip motion detection

Improved contrast sensitivity DVS and its application to event-driven stereo vision

Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays

FPGA based single cycle, reconfigurable router for NoC applications

A high resolution FPGA-based merged delay line TDC with nonlinearity calibration

An FPGA-based point target detection system using morphological clutter elimination

A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array

A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS

A 14-bit pipelined ADC with digital background nonlinearity calibration

A self-calibrated 10-bit 1 MSps SAR ADC with reduced-voltage charge-sharing DAC

Background calibration of time-interleaved ADC using direct derivative information

A time-interleaved ADC architecture exploiting correlations between samples

A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL

Analytical and experimental study of tuning range limitation in mm-wave CMOS LC-VCOs

Clock and data recovery module in 90nm for 10Gbps serial link with −18dB channel attenuation

Phase-locked loop architecture for enhanced voltage-controlled oscillator phase-noise suppression

A quadrature UWB frequency synthesizer with dynamic settling-time calibration

Artificial immune system based methods for spam filtering

An analogue implementation of the beta cell insulin release model

Parameter estimation of Hodgkin-Huxley neuronal model using dual extended Kalman filter

Face gender recognition with halftoning-based adaboost classifiers

Design optimisation of front-end neural interfaces for spike sorting systems

Recent advances in bridging time series and complex networks

Complex networks from time series: Capturing dynamics

Consensus in networked multi-agent systems via model predictive control with horizon one

A maximum likelihood approach to state estimation of complex dynamical networks with unknown noisy transmission channel

A node-weight equalization problem with circuit-based computations

A 1-bit Physically Unclonable Function based on a two-neurons CNN

Detecting community structure of networks using evolutionary coordination games

Overclocking datapath for latency-error tradeoff

Affine transformations for communication and reconfiguration optimization of loops on CGRAs

Pattern generation for Mutation Analysis using Genetic Algorithms

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing

Analytic modeling of interconnect capacitance in submicron and nanometer technologies

Fun examples for teaching linear and nonlinear circuits

Architecture and implementation of a development board for low-power education

The design of an audio power amplifier as a class project for undergraduate students

Integration of a wireless sensor network project for introductory circuits and systems teaching

LSMaker: A robotic platform for Engineering Education

An area-efficient shuffling scheme for AES implementation on FPGA

DPA resistance of charge-sharing symmetric adiabatic logic

High performance scalable elliptic curve cryptosystem processor in $GF(2^{m})$

FPGA implementation of a large-number multiplier for fully homomorphic encryption

A GPU implementation of the Montgomery multiplication algorithm for elliptic curve cryptography

Closed-form eigenvectors of the discrete Fourier Transform

High-performance RDFT design for applications of digital radio mondiale

A new involutory parametric transform and its application to image encryption

Closed-form design of fractional order differentiator using discrete cosine transform

A method for optimal SINR under non-i.i.d. interferences

A low power all-digital self-calibrated temperature sensor using 65nm FPGAs

A CMOS on-chip temperature sensor with −0.21°C 0.17 °C inaccuracy from −20 °C to 100 °C

A CMOS 8×8 SPAD array for Time-of-Flight measurement and light-spot statistics

Velocity saturation current-mode CMOS imaging sensor

A hybrid CMOS imager with sensing and energy harvesting capabilities

Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology

Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling

Current profile of a microcontroller to determine electromagnetic emissions

Synthesis of 3D clock tree with pre-bond testability

Practical methods for verifying removal of Trojan stable operating points

A structured DC analysis methodology for accurate verification of analog circuits

Channel characterization using jitter measurements

Electronically programmable test points for on-chip analog/digital measurements

High resolution ADC spectral test with known impure source and non-coherent sampling

A linearized voltage-controlled oscillator for dual-path phase-locked loops

An all-digital on-chip silicon oscillator with automatic VT range selection relative modeling

Simulating phase noise induced from cyclostationary noise sources

A 2.7-GHz digitally-controlled ring oscillator with supply sensitivity of 0.0014%-fDCO/1%-VDD using digital current-regulated tuning

Effects of numerical noise floor on the accuracy of time domain noise analysis in circuit simulators

A 0.5V 10GHz 8-phase LC-VCO Combining current-reuse and back-gate-coupling techniques consuming 2mW

On loop gain in linear networks

Modeling and fabrication of an RF MEMS variable capacitor with a fractal geometry

A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system

Nonlinear effects in electrostatic vibration energy harvesters: Current progress and perspectives

On-chip starter circuit for switched-inductor DC-DC harvester systems

Nonlinear dynamics in a graphene nanostructured device for energy harvesting

Impact-based electrostatic harvesters considered as a multi-source problem

Nonlinear vibration energy harvesting at work: An application for the automotive sector

Combined mechanical and circuit nonlinearities in electrostatic vibration energy harvesters

Chaotic behaviour in a three element memristor based circuit using fourth order polynomial and PWL nonlinearity

Spurious tones in digital delta sigma modulators with pseudorandom dither

Combination of exhaustive search and continuation method for the study of sinks in the Hénon map

Dynamical analysis of single-inductor dual-output DC-DC converters

A spiral learning approach to hardware description languages

Teaching electronic circuits online: Lessons from MITx's 6.002x on edX

A freshman level module in biometric systems

Efficient decision feedforward equalizer with parallelizable architecture

Delay element concept for Continuous Time Digital Signal Processing

On the efficient wireless power transfer in resonant multi-receiver systems

Interference analysis on Resonant Inductive Coupled Wireless Power Transfer links

Design methodology for inductive power transfer systems targeting high power implantable devices

Constant current charging in series-series compensated non-radiative wireless power link

A 60-GHz rectenna for monolithic wireless sensor tags

Demosaicking of Color Filter Array patterns using Quaternion Fourier Transform and low pass filter

Algorithm adaptive video deinterlacing using self-validation framework

Color constancy via chromaticity neutralization: From single to multiple illuminants

Fast and improved seam carving with strip partition and neighboring probability constraints

Adaptive watermarking technique based on human visual system and fuzzy inference system

Image denoising via Graph regularized K-SVD

A hybrid image restoration algorithm based on Projections Onto Convex Sets and Harmony Search

Computation of partial fractional derivative of digital image using discrete cosine transform

Adaptive parameter estimation for total variation image denoising

Improved total variation based image compressive sensing recovery by nonlocal regularization

Depth-aided exemplar-based hole filling for DIBR view synthesis

Cross-scene abnormal event detection

To exploit uncertainty masking for adaptive image rendering

A fast depth-map wedgelet partitioning scheme for intra prediction in 3D video coding

Error concealment for 3D video transmission

Fast vehicle detection based on feature and real-time prediction

Parallelizing video transcoding with load balancing on cloud computing

Speeding up the runtime performance for lossless image coding on GPUs with CUDA

Optimization of workload scheduling for multimedia cloud computing

Human emotion recognition using the adaptive sub-layer-compensation based facial edge detection

A spatial inter-view auto-regressive super-resolution scheme for multi-view image via scene matching algorithm

Recover image details from LDR photographs

A saliency detection model based on sparse features and visual acuity

A new Local-Main-Gradient-Orientation HOG and contour differences based algorithm for object classification

SIFT-based image super-resolution

Efficient view synthesis based error concealment method for multiview video plus depth

Fine registration of 3D point clouds with iterative closest point using an RGB-D camera

Influence Of camera imaging pipeline on stereo-matching quality: An experimental study

Low complexity image correction using color and focus matching for stereo video coding

Reducing computation complexity for disparity matching

New algorithm for minimax design of sparse IIR filters

Design and application of allpass filters with equiripple group delay errors

Tracking properties of complex adaptive notch filter for detection of multiple real sinusoids

An efficient matrix iterative algorithm for the WLS design of 2-D FIR filters

Low-complexity two-rate based multivariate impulse response reconstructor for time-skew error correction in m-channel time-interleaved ADCs

Detecting bifurcation types in DC-DC switching converters by duplicate symbolic sequence

Fast transient digitally controlled buck regulator with inductor current slew-rate boost

A new single-stage AC-DC converter for medical implant devices

Authentic mode-toggled detector with fast transient response under wide load range buck-boost converter

Macroscopic broadband loss characteristics of power transformer winding extracted by Vector Fitting Method

Ultra-low-power control systems for electrostatic energy harvesters

A study on MOSFET rectifiers maximum output voltage for RF power harvesting circuits

An approach for estimating mode shape for participation of inter-area oscillation mode

On measurement of synchronous phasors in electrical grids

A diffusive electro-equivalent Li-ion battery model

Support-driven sparse coding for face hallucination

Improved discriminant nearest feature space analysis for variable lighting face recognition

An empirical approach for digital currency forensics

Adaptive motion estimation order for frame rate up-conversion

Data hiding in error diffused color halftone images

Novel dual-threshold-voltage energy-efficient buffers for driving large extrinsic load capacitance

Efficient approaches to design a reversible floating point divider

A 2μW digital baseband core for wireless Micro-Neural-Interface in 0.18μm CMOS

Energy reduction of ultra-low voltage VLSI circuits by digit-serial architectures

Scalable low power digital filter architectures for varying input dynamic range

A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic

Efficient memory access methods for framebuffer-less video processing applications

A 0.4V 7T SRAM with write through virtual ground and ultra-fine grain power gating switches

High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit

Balancing Adder for error tolerant applications

Session chair index

2012 IEEE International Conference on Circuits and Systems (ICCAS)

2012 IEEE International Symposium on Circuits and Systems

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

2009 IEEE International Symposium on Circuits and Systems

2008 IEEE International Symposium on Circuits and Systems

2007 IEEE International Symposium on Circuits and Systems

2006 IEEE International Symposium on Circuits and Systems

2005 IEEE International Symposium on Circuits and Systems

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003.

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

1993 IEEE International Symposium on Circuits and Systems

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

1991., IEEE International Sympoisum on Circuits and Systems

IEEE International Symposium on Circuits and Systems

IEEE International Symposium on Circuits and Systems,

1988., IEEE International Symposium on Circuits and Systems

An empirical approach for digital currency forensics

Content Provider	IEEE Xplore Digital Library
Author	Yan, W.Q. Chambers, J.
Copyright Year	2013
Description	Author affiliation: Auckland Univ. of Technol., Auckland, New Zealand (Yan, W.Q.; Chambers, J.)
Abstract	The banknote manufacturing industry is shrouded in secrecy, fundamental mechanics of security components are closely guarded trade secrets. Currency forensics is the application of systematic methods to determine authenticity of questioned currency. However, forensic analysis is a difficult task requiring specially trained examiners, the most important challenge is automating the analysis process reducing human error and time. In this study, an empirical approach for automated currency forensics is formulated and a prototype is developed. A two parts feature vector is defined comprised of color features and texture features. Finally the note in question is classified by a Feedforward Neural Network (FNN) and a measurement of the similarity between template and suspect note is output.
Starting Page	2988
Ending Page	2991
File Size	1260032
Page Count	4
File Format	PDF
ISBN	9781467357609
ISSN	02714302
e-ISBN	9781467357623
DOI	10.1109/ISCAS.2013.6572507
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-19
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Forensics Support vector machine classification Image color analysis Feature extraction Training Histograms Accuracy
Content Type	Text
Resource Type	Article

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