NDLI: A high-throughput low-latency arithmetic encoder design for HDTV

Content Provider	IEEE Xplore Digital Library
Author	Yuan Li Shanghang Zhang Huizhu Jia Xiaodong Xie Wen Gao
Copyright Year	2013
Description	Author affiliation: Nat. Eng. Lab. for Video Technol., Peking Univ., Beijing, China (Yuan Li; Shanghang Zhang; Huizhu Jia; Xiaodong Xie; Wen Gao)
Abstract	In this paper, we propose a high-throughput low-latency arithmetic encoder (AE) design suitable for high definition (HD) real-time applications employing advanced video coding standards such as H.264/AVC or AVS and using a macroblock (MB) level pipeline. First, in order to derive the performance requirement on the AE, a buffer model in connected with which it is designed is thoroughly analyzed. Then, using joint algorithm-architecture optimization and multi-bin processing techniques, we introduce a novel binary arithmetic coder (BAC) architecture with throughput of 2~4 bins per cycle sufficient for real-time encoding. Furthermore, a hybrid context memory scheme is presented to meet the throughput requirement on the BAC. Simulation result shows that our design can support 1080p at 60 fps for AVS HDTV real-time coding with a bin rate up to 107K per MB line. Synthesized with the TSMC 0.13μm technology, the AE can run at 200MHz and costs 47.3K gates. By operating at 130MHz, the design is also verified in an AVS HD encoder on a Xilinx Virtex-6 FPGA prototype board for 1080p at 30 fps.
Starting Page	998
Ending Page	1001
File Size	511226
Page Count	4
File Format	PDF
ISBN	9781467357609
ISSN	02714302
e-ISBN	9781467357623
DOI	10.1109/ISCAS.2013.6572017
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-19
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Throughput Context Video coding Encoding Random access memory Bit rate Real-time systems
Content Type	Text
Resource Type	Article

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