NDLI: Memory-efficient scalable video encoder architecture for multi-source digital home environment

Content Provider	IEEE Xplore Digital Library
Author	Tsung-Han Tsai Zong-Hong Li Hsueh-Yi Lin Li-Yang Huang
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. Eng., Nat. Central Univ., Taoyuan, Taiwan (Tsung-Han Tsai; Zong-Hong Li; Hsueh-Yi Lin; Li-Yang Huang)
Abstract	In this paper, a memory-efficient and low-complexity architecture is proposed for the scalable video encoder, achieving the requirement of the multi-source digital home environment. The proposed very-large-scale integration architecture of the scalable video encoder is implemented in TSMC 0.18-μm 1P6M CMOS technology. The proposed hardware is synthesized under 0.18-μm CMOS technology; resulting throughput is 93.3M samples/sec, occupying 182K gates. Resulting power dissipation is 42.13 mW, operating at 150 MHz clock source. The performance of proposed work (the throughput) meets 1080p@30 fps real-time encoding, constrained by wireless high definition video interface for mobile environment.
Starting Page	685
Ending Page	688
File Size	1201946
Page Count	4
File Format	PDF
ISBN	9781467357609
ISSN	02714302
e-ISBN	9781467357623
DOI	10.1109/ISCAS.2013.6571939
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-19
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete wavelet transforms Computer architecture Encoding Very large scale integration Context Image coding Codecs image compression Lossless compression quality driven bit plane sequencer size scalability SNR scalability video compression
Content Type	Text
Resource Type	Article

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