NDLI: Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary Domain

Content Provider	IEEE Xplore Digital Library
Author	Vasudevan, V. Sheshadri, V. Krishnan, R.S. Patel, K.S.V.
Copyright Year	2011
Abstract	The complexity of programmable logic design has increased ever since its conception because of the increased focus on seamless integration of design creation. Interconnections, which occupy 60 to 90% of the chip area, play a vital role in deciding the power and delay in such designs. Hence there is an increased focus on Multi-Valued Logic, because of its inherent ability to reduce the number of interconnections. In this paper, we present the design of (n=15, k=13) Reed Solomon code algorithm for advanced Redundant Array of Independent Disks (RAID) system in quaternary domain, to tolerate multiple disk failures. We present two designs to implement the algorithm on a FPGA- a heterogeneous design consisting of quaternary and binary circuits, a complete quaternary design. The first design performs all computations using only binary EX-OR gates. This design requires more EX-OR operations than the binary counterpart. This number is a function of the generator polynomial used for encoding. The second design based on quaternary look-up tables is efficient and can be easily implemented. The look-up tables are in turn based on quaternary multiplexers that can be further optimized by reducing the feature size.
Starting Page	307
Ending Page	312
File Size	558804
Page Count	6
File Format	PDF
ISBN	9781457708039
ISSN	21592477
DOI	10.1109/ISVLSI.2011.75
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Polynomials Algorithm design and analysis Table lookup Generators Reed-Solomon codes Integrated circuit interconnections Logic gates disk failure quaternary logic RAID Galois Reed Solomon erasure failure look-up table encoder decoder
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Low Complexity Design of Reed Solomon Code Algorithm for Advanced RAID System

Low-power design of Reed-Solomon encoders

TIP-Code: A Three Independent Parity Code to Tolerate Triple Disk Failures with Optimal Update Complextiy

Novel Polynomial Basis and Its Application to Reed-Solomon Erasure Codes

A 40-MHz encoder-decoder chip generated by a Reed-Solomon code compiler

High throughput FPGA implementation of Reed-Solomon Encoder for Space Data Systems

Novel pipelined interpolator for low-complexity chase soft-decision Reed-Solomon decoder

Universal Architectures for Reed-Solomon Error-and-Erasure Decoder

Design of reed-solomon encoder/decoder using modified euclid's algorithm

Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary Domain

Similar Documents

A Low Complexity Design of Reed Solomon Code Algorithm for Advanced RAID System

Low-power design of Reed-Solomon encoders

TIP-Code: A Three Independent Parity Code to Tolerate Triple Disk Failures with Optimal Update Complextiy

Novel Polynomial Basis and Its Application to Reed-Solomon Erasure Codes

A 40-MHz encoder-decoder chip generated by a Reed-Solomon code compiler

High throughput FPGA implementation of Reed-Solomon Encoder for Space Data Systems

Novel pipelined interpolator for low-complexity chase soft-decision Reed-Solomon decoder

Universal Architectures for Reed-Solomon Error-and-Erasure Decoder

Design of reed-solomon encoder/decoder using modified euclid's algorithm

Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary Domain