NDLI: High-order multi-bit incremental converter with Smart-DEM algorithm

Content Provider	IEEE Xplore Digital Library
Author	Yao Liu Bonizzoni, E. Maloberti, F.
Copyright Year	2013
Description	Author affiliation: Dipt. di Ing. Ind. e dell'Inf., Univ. of Pavia, Pavia, Italy (Yao Liu; Bonizzoni, E.; Maloberti, F.)
Abstract	This paper describes the design method for highorder multi-bit incremental converters aiming at high resolution (> 14 bits) with Smart-DEM algorithm. Traditional $2^{nd}$ and $3^{rd}-order$ incremental ADCs use 1-bit quantizer. These structures lead to long conversion time for each sample to achieve the expected resolution and high power consumption due to the large output swing of the op-amps. Also, the fractional coefficients along the accumulation path that avoid instability degrade the performance. On the contrary, modulators employing multi-bit quantizer and DAC do not suffer from these problems. Although the mismatch of unity elements in the DAC causes non-linearity issue, this can be suppressed by Smart-DEM algorithm. Because the Smart-DEM algorithm is quite compact and easy to implement, the modulator benefits extra bits performance directly from the multi-bit DAC with affordable digital circuits overhead. In this paper several structures for incremental ADCs utilizing multi-bit quantizer are presented. The positive-and-negative DAC and the Smart-DEM algorithm are explained. With 3-bit quantizer, the simulation results show that the $2^{nd}-order$ incremental ADC obtains 18-bit resolution with 256 clock periods.
Starting Page	157
Ending Page	160
File Size	591617
Page Count	4
File Format	PDF
ISBN	9781467357609
ISSN	02714302
e-ISBN	9781467357623
DOI	10.1109/ISCAS.2013.6571806
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-19
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Modulation Linearity Sigma-delta modulation Algorithm design and analysis Signal resolution Guidelines
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

High-Order Multi-Bit Incremental Converter with Smart-DEM Algorithm

A multi-bit cascaded sigma-delta modulator with an oversampled single-bit DAC

Linearity Enhancement of Multi-bit \Delta\Sigma A/D and D/A Converters Using Data Weighted Averaging (1995)

High resolution multi-bit sigma-delta modulator architecture

Multi-bit Sigma-Delta TDC Architecture for Digital Signal Timing Measurement

A 14-Bit 5MS/s Continuous-Time Delta-Sigma A/D Modulator

A high-resolution low-power and multi-bit incremental converter with smart-DEM

A high-resolution low-power and multi-bit incremental converter with smart-DEM

Multi-bit sigma-delta TDC architecture with self-calibration

High-order multi-bit incremental converter with Smart-DEM algorithm

Similar Documents

High-Order Multi-Bit Incremental Converter with Smart-DEM Algorithm

A multi-bit cascaded sigma-delta modulator with an oversampled single-bit DAC

Linearity Enhancement of Multi-bit \Delta\Sigma A/D and D/A Converters Using Data Weighted Averaging (1995)

High resolution multi-bit sigma-delta modulator architecture

Multi-bit Sigma-Delta TDC Architecture for Digital Signal Timing Measurement

A 14-Bit 5MS/s Continuous-Time Delta-Sigma A/D Modulator

A high-resolution low-power and multi-bit incremental converter with smart-DEM

A high-resolution low-power and multi-bit incremental converter with smart-DEM

Multi-bit sigma-delta TDC architecture with self-calibration

High-order multi-bit incremental converter with Smart-DEM algorithm