NDLI: Packaging technologies for supercomputer system

Content Provider	IEEE Xplore Digital Library
Author	Hamaguchi, H. Watari, T. Dohya, A.
Copyright Year	1991
Description	Author affiliation: NEC Corp., Tokyo, Japan (Hamaguchi, H.; Watari, T.; Dohya, A.)
Abstract	The NEC SX-3 Model 44 supercomputer system has a maximum performance of 5.5 Gflops for the uniprocessor and 22 Gflops for the quad processor. The authors discuss packaging technology for the SX-3, which allows reduction of signal propagation delays between LSIs. It consists of 3 levels. The first level uses high-density connection technology that allows full exploitation of high-speed LSI chips. The authors developed an advanced chip carrier for this purpose referred to as the FTC (flipped TAB carrier). The second level is the multichip package level containing high-density FTCs prepared at the first level. The third level is a board level. The main focus is shortening of connecting wires between the MCPs (multichip packages). Other measures used were adoption of the FTC as an LSI chip carrier that allows implementation of an LSI with multiple terminals and high power, and adoption of a ceramic+polyimide structure as a multilayer substrate that yields high speed and high-density wiring.<>
Starting Page	2292
Ending Page	2295
File Size	282173
Page Count	4
File Format	PDF
ISBN	0780300505
DOI	10.1109/ISCAS.1991.176823
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-06-11
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Packaging Supercomputers Large scale integration National electric code Propagation delay Joining processes Wires Power measurement Velocity measurement Semiconductor device measurement
Content Type	Text
Resource Type	Article

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