NDLI: Prototype chip set for systolic wave digital filters employing optimal two phase clocking

Content Provider	IEEE Xplore Digital Library
Author	Summerfield, S.
Copyright Year	1991
Description	Author affiliation: Dept. of Eng., Warwick Univ., Coventry, UK (Summerfield, S.)
Abstract	A general method for the implementation of one-dimensional word-level systolic arrays using bit-level systolic arrays is developed. The relative merits of single- and two-phase clocking are examined. An analysis indicates an advantage of two-phase clocking for the systems studied in respect to area usage and potential speed. The results are applied to the design of a prototype unit-element cascade wave digital filter whose bit-sliced design is partitioned into a set of chips and fabricated using gate array technology, producing the first bit-level systolic wave digital filter in hardware. Test results verify the design and give the relationship between the systolic cell delay and the system clock rate. The system is capable of simple filtering operations at 2 MHz, independent of the data wordlength.<>
Starting Page	2196
Ending Page	2199
File Size	277559
Page Count	4
File Format	PDF
ISBN	0780300505
DOI	10.1109/ISCAS.1991.176731
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-06-11
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Prototypes Digital filters Clocks Delay Phased arrays Pipeline processing Feedback loop Systolic arrays Master-slave Timing
Content Type	Text
Resource Type	Article

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