NDLI: VLSI neurocomputing with analog programmable chips and digital systolic array chips

Content Provider	IEEE Xplore Digital Library
Author	Sheu, B.J.
Copyright Year	1991
Description	Author affiliation: Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA (Sheu, B.J.)
Abstract	Progress in the system architectures and VLSI implementations of analog and digital electrical neuroprocessors is described. In analog programmable neural chips, electronic neurons and synapses are realized by operational amplifiers and synthesized resistors, respectively. The synapse weight information is stored in the dynamically refreshed capacitors for medium-term storage or in the floating gates of double-polysilicon transistors for long-term storage. The adjustability of the voltage gain in the electronic neurons allows the implementation of hardware annealing to search for optimal solutions in network retrieving and learning processes very efficiently. In digital neural chips, systolic architecture is used to process the data in a pipelined format for the one-dimensional ring or two-dimensional mesh configurations. Various learning rules are directly supported in the digital approach. In many high-speed image processing applications, numerical computation can be done efficiently using an analog approach, while long-distance communication is best achieved through the digital approach.<>
Starting Page	1267
Ending Page	1270
File Size	601346
Page Count	4
File Format	PDF
ISBN	0780300505
DOI	10.1109/ISCAS.1991.176600
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-06-11
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Neural network hardware Neurons Operational amplifiers Network synthesis Resistors Capacitors Voltage Annealing Computer architecture
Content Type	Text
Resource Type	Article

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