NDLI: Analysis and design of regular structures for robust dynamic fault testability

Content Provider	IEEE Xplore Digital Library
Author	Bryan, M.J. Devadas, S. Keutzer, K.
Copyright Year	1991
Description	Author affiliation: MIT, Cambridge, MA, USA (Bryan, M.J.; Devadas, S.)
Abstract	The authors analyze various regular structures such as adders, arithmetic logic units, comparators, multipliers, and parity generators to determine if they are testable for dynamic faults, or how they can be modified to be testable for dynamic faults while still maintaining good area and performance characteristics. In addition to minimizing the area and delay, another key consideration is to get designs which can be scaled to an arbitrary number of bits while still maintaining complete testability. In each case, the emphasis is on obtaining circuits which are fully path-delay-fault testable. In the process of design modification to produce fully robustly testable structures, the authors derive a number of new composition rules that allow cascading individual modules while maintaining robust testability under dynamic fault models. Where complete robust path-delay-fault testability is not achievable without significant area or speed penalties, methods of obtaining circuits that are fully testable in weaker fault models, such as transistor stuck-open-fault and robust gate-delay-fault, are analyzed.<>
Starting Page	1968
Ending Page	1971
File Size	551286
Page Count	4
File Format	PDF
ISBN	0780300505
DOI	10.1109/ISCAS.1991.176795
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-06-11
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Robustness Circuit testing Circuit faults Logic testing Performance analysis Adders Arithmetic Character generation Delay Process design
Content Type	Text
Resource Type	Article

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