NDLI: Two-dimensional digital filtering using a linear processor array

Content Provider	IEEE Xplore Digital Library
Author	Aboelaze, M.A. Lee, D.-L. Wah, B.W.
Copyright Year	1991
Description	Author affiliation: Dept. of Comput. Sci., York Univ., North York, Ont., Canada (Aboelaze, M.A.; Lee, D.-L.)
Abstract	A linear VLSI array is presented for implementing the M-th order 2-dimensional FIR and IIR digital filters. The linear array consists of k M processor elements (PEs). Each PE consists of a control unit, ALU, storage unit, and input/output buffers. The control unit contains microinstructions to be executed by the ALU. Its design is simple and is capable of executing a few instructions such as reading a word from the memory, storing a result in the memory, and performing simple arithmetic operations. The storage element contains O(N) words and can be accessed by the ALU. Input/output buffers are used for receiving data from other PEs and holding results before they are sent to neighboring PEs. The resulting speedup is O(kM), where k is a parameter governed by the tradeoff between the cost of the array and its speedup.<>
Starting Page	2943
Ending Page	2946
File Size	352158
Page Count	4
File Format	PDF
ISBN	0780300505
DOI	10.1109/ISCAS.1991.176162
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-06-11
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital filters Nonlinear filters Filtering Finite impulse response filter Very large scale integration IIR filters Costs Systolic arrays Buffer storage Computer vision
Content Type	Text
Resource Type	Article

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