NDLI: VLSI implementation of neural networks with application to signal processing

Content Provider	IEEE Xplore Digital Library
Author	Jabri, M. Pickard, S. Leong, P. Rigby, G. Jiang, J. Flower, B. Henderson, P.
Copyright Year	1991
Description	Author affiliation: Sydney Univ., NSW, Australia (Jabri, M.; Pickard, S.; Leong, P.; Rigby, G.; Jiang, J.; Flower, B.; Henderson, P.)
Abstract	Mapping a functional neural network model to analog sub-threshold MOS technology is a challenging task, and requires careful architectural, system level and circuit level consideration, with respect to the constraints inherent in this technology. The authors present their experience in this mapping process. The artificial neural network systems addressed are programmable ones facilitating learning either on or off chip. The authors consider multi-layer feedforward networks, although the techniques can be easily adapted to recurrent networks. A multi-layer learning algorithm suitable for analog sub-threshold implementation is presented. The authors discuss system level issues, describe circuits of neurons and synapses that have been designed, and present fabrication results.<>
Starting Page	1275
Ending Page	1278
File Size	336534
Page Count	4
File Format	PDF
ISBN	0780300505
DOI	10.1109/ISCAS.1991.176602
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-06-11
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Neural networks Signal processing Hardware Neurons Artificial neural networks Energy consumption Signal processing algorithms Circuits Wires
Content Type	Text
Resource Type	Article

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