NDLI: A method for sizing transistors in CMOS op-amps

Content Provider	IEEE Xplore Digital Library
Author	Smith, M.H. Walczowski, L.T. Waller, W.A.J. Howard, D.
Copyright Year	1991
Description	Author affiliation: Electron. Eng. Lab., Kent Univ., Canterbury, UK (Smith, M.H.; Walczowski, L.T.; Waller, W.A.J.; Howard, D.)
Abstract	The authors present a method for automatically calculating the size of the transistors and passive components in a CMOS op-amp given the specification and loading of the op-amp. The method is similar to that used in the OASYS program in that it uses no simulation. Like the OASYS method, the authors estimate the sizes and then calculate the parasitics. The parasitics calculated are then used to recalculate the sizes. This process continues until the parasitics change only little. Unlike OASYS, the authors separated the sizing method from the model of the transistor. This means one is able to use any transistor model to size the transistors, and, because the method does not use simulation and so makes less calls of the model equations, the model used can be more complicated than that used for simulation.<>
Starting Page	2016
Ending Page	2019
File Size	336749
Page Count	4
File Format	PDF
ISBN	0780300505
DOI	10.1109/ISCAS.1991.176061
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-06-11
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Operational amplifiers Computational modeling Circuit simulation Semiconductor device modeling Phase estimation Voltage Laboratories CMOS process Size control Process control
Content Type	Text
Resource Type	Article

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