NDLI: A stochastic model for fault propagation, in combinational circuits

Content Provider	IEEE Xplore Digital Library
Author	Sastry, S. Majumdar, A.
Copyright Year	1991
Description	Author affiliation: Dept. of EE-Syst., Univ. of Southern California, Los Angeles, CA, USA (Sastry, S.; Majumdar, A.)
Abstract	The authors present a new stochastic model for fault propagation in combinational circuits that is sensitive to the structural characteristics of the circuit. Under random testing, fault propagation through a circuit is modeled as a branching process. Due to the presence of fanout, a fault on a gate at level l, once activated, will generate a number of copies of itself, called descendants, at level l+1. Similarly, due to the presence of reconvergent fanout, a fault may cease to propagate. An activated fault is detected if at least one of its descendants is active at the primary outputs. For a fault on a gate at level l, the authors present basic results on the distribution of the number of next-level descendants and the number of kth-level descendants, k>or=l. The importance of these results lies in the fact that they are sensitive to the circuit structure and play a basic role in design for testability.<>
Starting Page	1964
Ending Page	1967
File Size	409209
Page Count	4
File Format	PDF
ISBN	0780300505
DOI	10.1109/ISCAS.1991.176794
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-06-11
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stochastic processes Circuit faults Combinational circuits Circuit testing Observability Controllability Fault detection Design for testability Electrical fault detection Event detection
Content Type	Text
Resource Type	Article

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