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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nwankpa, C. Deese, A. Qingyan Liu St Leger, A. Yakaski, J. |
| Copyright Year | 2006 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA (Nwankpa, C.; Deese, A.; Qingyan Liu; St Leger, A.; Yakaski, J.) |
| Abstract | This paper addresses modeling issues behind the development of a hardware analog emulator of power system behavior referred to as a power system on a chip (PSoC). The paper reviews various problems and proposed solutions encountered from the design stage to PC-board hardware implementation to anticipated VLSI implementation. It has already been noted that using analog emulation for power system analysis allows for reduction in computation time, without significant loss in accuracy, compared to numerical methods. This is further validated in this paper through observations obtained from comparative runs between software and analog hardware environments |
| Sponsorship | The Inst. of Electr. and Electron. Eng., Inc. Circuits and Syst. Soc. (IEEE CASS) |
| Starting Page | 4 |
| Ending Page | 742 |
| File Size | 3815725 |
| Page Count | 739 |
| File Format | |
| ISBN | 0780393899 |
| DOI | 10.1109/ISCAS.2006.1692691 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-05-21 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Power systems Analog computers Power system modeling Power system simulation Power system analysis computing Very large scale integration Digital simulation Hardware Algorithm design and analysis Concurrent computing |
| Content Type | Text |
| Resource Type | Article |
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