NDLI: Implementation of space-efficient voltage-insensitive capacitances in integrated circuits

Content Provider	IEEE Xplore Digital Library
Author	Chunyan Wang
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que. (Chunyan Wang)
Abstract	In this paper, an approach of implementing voltage-insensitive and space-efficient capacitances has been proposed. It tackles capacitive elements related to the thin dielectric layers available in fabrication technologies of integrated circuits. It makes the use of the voltage-independent ones, such as the overlap capacitances of MOS transistors, and the voltage-dependency of the capacitances attached to the same circuit nodes are minimized by device geometric sizing and voltage biasing. In the case of using the MOS transistor gate dielectric layer, the capacitance is scaled by the width of the gate area of the transistor employed. As the transistor feature size is of sub-micron, the unit capacitance can be very small and the capacitances can be scaled easily and precisely, which facilitates a significant down-scale of the circuit geometric dimension, operation delay and, at the same time, power dissipation. As an example of application of the proposed approach, a charge-mode parallel D/A converter is proposed in this paper
Sponsorship	The Inst. of Electr. and Electron. Eng., Inc. Circuits and Syst. Soc. (IEEE CASS)
Starting Page	4
Ending Page	1879
File Size	370995
Page Count	1876
File Format	PDF
ISBN	0780393899
DOI	10.1109/ISCAS.2006.1692975
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-21
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Capacitance Circuits Switches MOSFETs Dielectric devices Fabrication Space technology CMOS technology Capacitors
Content Type	Text
Resource Type	Article

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