NDLI: A power planning model for implantable stimulators

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2015 IEEE International Symposium on Circuits and Systems (ISCAS)

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

2012 IEEE International Conference on Circuits and Systems (ICCAS)

2012 IEEE International Symposium on Circuits and Systems

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

2009 IEEE International Symposium on Circuits and Systems

2008 IEEE International Symposium on Circuits and Systems

2007 IEEE International Symposium on Circuits and Systems

2006 IEEE International Symposium on Circuits and Systems

2006 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 06CH37717C)

Table of contents

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Digit-serial/parallel multipliers with improved throughput and latency

Multiplier reduction tree with logarithmic logic depth and regular connectivity

Implementation of a high-speed low-power 32-bit adder in 70nm technology

A 372 ps 64-bit adder using fast pull-up logic in 0.18-/spl mu/m CMOS

Low power binary addition using carry increment adders

Ultra-low voltage VLSI: are we there yet?

Ultra-low voltage nano-scale embedded RAMs

Energy efficient design for subthreshold supply voltage operation

Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits

Localized microarchitecture-level voltage management

A two-level hybrid select logic for wide-issue superscalar processors

A compact CPU architecture for sensor signal processing

Fast bit permutation unit for media enhanced microprocessors

Fast and low-power processor front-end with reduced rename logic circuit complexity

A versatile computation module for adaptable multimedia processors

Inverting closed-loop amplifier architecture with reduced gain error and high input impedance

A rail to rail, slew-boosted pre-charge buffer

A CMOS transconductor with 90 dB SFDR and low sensitivity to mismatch

Linear compact CMOS OTA with multidecade tuning, -62dB IM3, -75dB SFDR, constant input range and two independent degrees of freedom for gain adjustment

New CMOS fully differential transconductor and its application

An FCC compliant pulse generator for IR-UWB communications

A 5-GHz combined oscillator/mixer

A broadband indirect-feedback power-to-current LNA

A temperature compensated linear output RF amplifier with programmable gain control

2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop

DDL-based calibration techniques for timing errors in current-steering DACs

A 12-bit current steering DAC for cryogenic applications

A 14-bit D/A-converter with digital calibration

High-speed pipelined DAC architecture using Gray coding

Dynamic calibration of current-steering DAC

A Kalman filter based on wavelet filter-bank and psychoacoustic modeling for speech enhancement

A new Kalman filter-based algorithm for adaptive coherence analysis of non-stationary multichannel time series

A new adaptive Kalman filter-based subspace tracking algorithm and its application to DOA estimation

Equivalent output-filtering using fast QRD-RLS algorithm for burst-type training applications

A modified particle swarm optimization algorithm for adaptive filtering

Low complexity architecture design of MDCT-based psychoacoustic model for MPEG 2/4 AAC encoder

An efficient MFCC extraction method in speech recognition

A bit-serial approximate min-sum LDPC decoder and FPGA implementation

Architecture design and VLSI hardware implementation of image encryption/decryption system using re-configurable 2D Von Neumann cellular automata

A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme

System aspects of a bionic eyeglass

Detection of a preseizure state in epilepsy: signal prediction by maximally weakly nonlinear networks?

Towards autonomous adaptive behavior in a bio-inspired CNN-controlled robot

Towards an ultra low power chemically inspired electronic beta cell for diabetes

Information and image processing through bio-inspired oscillatory cellular nonlinear networks

A reconfigurable architecture for the FFT operator in a software radio context

Is there life after bit error rate or before?

Generalized semi-blind channel estimator for TCM-OFDM system

Low-complexity adaptive array for DS/CDMA code acquisition

Robust front-end design for ultra wideband systems

A time-domain gradient-detection architecture for VLSI analog motion sensors

An adaptive CMOS imager with time-based compressive active-pixel response

Fabrication of a thin film micro polarization array

Image sensor with focal plane extraction of polarimetric information

A second-generation single-chip stereo imager

Experimental confirmation of n-scroll hyperchaotic attractors

A current-mode chaotic oscillator

Chaos in delay locked loop

Generating multi-scroll chaotic attractors via threshold control

Hash function based on chaotic neural networks

Operation of class DE amplifier outside optimum condition

High-frequency DC-DC conversion : fact or fiction

Sub-optimum operation of class E amplifier with nonlinear shunt capacitance at any duty cycle

A comparison of output envelope waveforms of the delta-sigma modulated class D series resonant inverter

A family of PWM based sliding mode voltage controllers for basic DC-DC converters

Set-membership affine projection algorithm with variable data-reuse factor

Set-membership filtering strategies for multipulse coding

Adaptive projected subgradient method and its applications to robust signal processing

Robustness optimization of parametric speech watermarking

A set-membership NLMS algorithm with time-varying error bound

A high-speed Reed-Solomon decoder for correction of both errors and erasures

A low energy VLSI design of random block interleaver for 3GPP turbo decoding

Design and implementation of efficient Reed-Solomon decoders for multi-mode applications

VLSI architecture for 4 /spl times/ 4 16-QAM V-BLAST decoder

Lossless data compression core design for integrated space data and communication system-on-chip

A new low cost and reconfigurable RSA crypto-processor

A new dual-field elliptic curve cryptography processor

An optimal normal basis elliptic curve cryptoprocessor for inductive RFID application

Low power compact design of ARIA block cipher

A novel concept for stateless random bit generators in cryptographic applications

Average lengths of wire routing under M-architecture and X-architecture

Performance and power aware buffered tree construction

Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing

A one-shot projection method for interconnects with process variations

Channel based routing in channel-less circuits

A low-voltage adaptive switched-current SDM for bio-acquisition microsystems

An ECG measurement IC using driven-right-leg circuit

Bidirectional telemetry for implantable systems

Movement recognition and strain lecture algorithm for fracture monitoring system

A new VLSI structure for an improved near-lossless color image compression algorithm inside wireless endoscopy capsule

Probability updating-based adaptive hybrid coding (PUAHC)

Statistical rate-distortion estimation for H.264/AVC coders

Enhanced spatial error concealment with directional entropy based interpolation switching

A new approach to secure distributed storage, sharing and dissemination of digital image

Low power architectures using localised non-volatile memory and selective power shut-down

A 2-GHz integrated CMOS reflective-type phase shifter with 675/spl deg/ control range

Triangular systolic array with reduced latency for QR-decomposition of complex matrices

Grouped multiuser diversity in multiuser MIMO systems exploiting spatial multiplexing

Hybrid order detection algorithm for V-BLAST system employing adaptive modulation

A pipelined VLSI architecture for a list sphere decoder

A semiblind receiver for space-time block-coded downlink multirate DS-CDMA systems

Set-membership affine projection algorithm for echo cancellation

A semiblind receiver based upon multiple constrained subspace MUD for long-code downlink multirate DS-CDMA systems

A minimum transmission power AM-MIMO system

Non-uniform subband adaptive filtering with critical sampling

An analysis of matching in the Tau cell log-domain filter

A single chip image sensor embedded smooth spatial filter with A/D conversion

Modeling the impact of light on the performance of polycrystalline thin-film transistors at the sub-threshold region

Minimization of total area in integrated active RC filters

Rail-to-rail tunable CMOS V-I converter

Current-mode and voltage-mode quadrature oscillator employing multiple outputs CCIIs and grounded capacitors

Method for design of analog group delay equalizers

Possible benefits of moderate inversion for MOSFET transconductors

Gramian-preserving frequency transformation for linear continuous-time state-space systems

High-gain current amplifiers for low-power MOSFET-C filters

Error-resilience packet scheduling for low bit-rate video streaming over wireless channels

XML-based customization along the scalability axes of H.264/AVC scalable video coding

Exploring reusable frame buffer data for MPEG-4 video decoding

Fast mode decision and motion estimation for H.264 (FMDME)

On a design of crossroad switches for low-power on-chip communication architectures

Optimum sizing of power grids for IR drop

Optimum wire tapering for minimum power dissipation in RLC interconnects

On-die decoupling capacitance: frequency domain analysis of activity radius

Power supply variation effects on timing characteristics of clocked registers

Coupling aware RLC-based clock routings for crosstalk minimization

An automatic three-dimensional human behavior analysis system for video surveillance applications

Quickest change detection for health-care video surveillance

Real-time event detection and its application to surveillance systems

Video-based face authentication using appearance models and HMMs

Developing smart video semantic sensors

An FPGA implementation of the flexible triangle search algorithm for block based motion estimation

An FPGA based SIMD processor with a vector memory unit

AES as stream cipher on a small FPGA

A FPGA implementation of an elliptic curve cryptosystem

Performance and routability improvements for routability-driven FPGA routers

High-precision, fast current source for large-area current-programmed a-Si flat panels

Dielectric absorption of low-k materials: extraction, modelling and influence on SAR ADCs

Current source calibration by combination selection of minimum sized devices

Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors

An analog storage cell with 5e/sup -//sec leakage

Analysis of power supply gain of CMOS bandgap references

A 1.5-V 10-ppm//spl deg/C 2nd-order curvature-compensated CMOS bandgap reference with trimming

Characterization of a current-mode bandgap circuit structure for high-precision reference applications

Explicit characterization of bandgap references

A new temperature-compensated CMOS bandgap reference circuit for portable applications

A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator

An optimal architecture for a multimode ADC, based on the cascade of a /spl Sigma//spl Delta/ modulator and a flash converter

Design of a 1.2-V cascade continuous-time /spl Delta//spl Sigma/ modulator for broadband telecommunications

Stability analysis of higher-order delta-sigma modulators using the describing function method

Double-sampled cascaded sigma-delta modulator topologies for low oversampling ratios

A new integrated approach to the design of low-complexity FIR filters

The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity

An algorithm for optimal terms allocation for fixed point coefficients of FIR filter

Maximum likelihood disjunctive decomposition to reduced multirooted DAG for FIR filter design

Improved differential coefficients-based low power FIR filters. Part I. Fundamentals

Assessment of parameter extraction methods for integrated inductor design and model validation

Automatic synthesis of CMOS RF front-ends

An analytical propagation delay model with power supply noise effects

Symbolic analysis and optimization of piezo-electromechanical systems

Automated design and layout generation for switched current circuits

A stimulator output stage with capacitor reduction and failure-checking techniques

A nanowatt bandgap voltage reference for ultra-low power applications

CMOS variable-gain wide-bandwidth CMFB-free differential current feedback amplifier for ultrasound diagnostic applications

A 0.9 V rail-to-rail constant g/sub m/ amplifier for implantable biomedical applications

DSP architecture for cochlear implants

Pulse generator for UWB communication and radar applications with PPM and time hopping possibilities

Quadrature-DAC based pulse generation for UWB pulse radio transceivers

Fully integrated sub-microWatt CMOS ultra wideband pulse-based transmitter for wireless sensors networks

Sine wave as a correlating signal for UWB radio

An all CMOS 743 MHz variable gain amplifier for UWB systems

Unequal error protection for MIMO systems with a hybrid structure

Spatio-temporal boundary matching algorithm for temporal error concealment

Non-causal error control for wireless video streaming with noncoherent signaling

Three-loop temporal interpolation for error concealment of MDC

Multi-source multi-path video streaming over wireless mesh networks

A brief overview of multi-scroll chaotic attractors generation

2D scroll grid attractors from pulse-excited nonautonomous circuits

Hyperchaotic 3D-scroll attractors via Hermite polynomials: the Adomian decomposition approach

Design and implementation of multi-directional grid multi-torus chaotic attractors

Multi-scroll and hypercube attractors from Josephson junctions

Power systems as dynamic networks

Investigating power system stability limits

Voltage stability and voltage recovery: effects of electric load dynamics

Computation of unstable limit cycles in large-scale power system models

Power system on a chip (PSoC)

Global exponential stability of generalized neural networks with time-varying delays

A neural network for convex optimization

A biomimetic CMOS synapse

Global stability of a recurrent neural network for solving pseudomonotone variational inequalities

A result on global convergence in finite time for nonsmooth neural networks

A mesochronous pipeline scheme for high performance low power digital systems

Delay uncertainty due to supply variations in static and dynamic full adders

Adaptive timing for analysis of skew tolerance

Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking

High performance single clock cycle CMOS comparator

Parity-based on-line detection for a bit-parallel systolic dual-basis multiplier over GF(2/sup m/)

A fast dual-field modular arithmetic logic unit and its hardware implementation

A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory

Approximation of elementary functions using a weighted sum of bit-products

Compressed symmetric tables for accurate function approximation of reciprocals

Algorithms for generation of quaternary fixed polarity arithmetic spectra

System-level verification on high-level synthesis of dataflow graph

An efficient mechanism to provide full visibility for hardware debugging

Sub-faults identification for collapsing in diagnosis

Behavioral synthesis with SystemC and PSL assertions for interface specification

Hybrid discretization in power converters' digital controller design

State-space averaging of switched-inductor-cell for PWM dc-dc converters considering conduction losses in both operational modes

Modeling of switched DC-DC converters by mixed s-z description

On discretizing linear passive controllers

One-cycle control of converters operating in DCM

A statistical approach to localize passive RFIDs

Real-time acoustic monitoring using wireless sensor motes

Supercritical stability in a sonar receiver circuit

A sensor system on chip for wireless microsystems

Spike response properties of an AER EAR

A tunable 0.5-1.3 GHz CMOS 2nd order bandpass filter with 50/spl Omega/ input-output impedance matching

A CMOS bandpass filter with wide-tuning range for wireless applications

A low power, transverse analog FIR filter for feed forward equalization of gigabit Ethernet

FPGA implementation of FIR filter using M-bit parallel distributed arithmetic

A widely tunable active RF filter topology

Quaternionic formulation of the first regularity for four-band paraunitary filter banks

Design of signal-adapted nonuniform filter banks using tree structure

Robust design of hybrid filter bank A/D converters using second order cone programming

On the theory and design of a class of recombination nonuniform filter banks with low-delay FIR and IIR filters

Characterization and design of oversampled linear phase filterbanks with rational oversampling ratio

A low-voltage operational amplifier with high slew-rate for sigma-delta modulators

High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit

Active reversed nested Miller compensation for three-stage amplifiers

General model for delayed feedback and its application to transimpedance amplifier's bandwidth optimization

A new low-voltage CMOS unity-gain buffer

Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP

A new motion and disparity vector prediction technique for H.264 based stereoscopic video coding

Wavelet based detection of moving tree branches and leaves in video

Adaptive exposure control and real-time image fusion for surveillance systems

An open-source based DSP with enhanced multimedia-processing capacity for embedded applications

A micropower vision processor for parallel object positioning and sizing

Texture segregation employing orientation-selective analog multi-chip vision system

High-speed image processing with AER-based components

Address-event image sensor network

Normal flow measurement visual motion sensor

Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches

Set-sweep programming pulse for phase-change memories

A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM

A zero-mask one-time programmable memory array for RFID applications

DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs

Semi-symbolic modeling and simulation of circuits and systems

A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers

Embedded mixed-signal systems: new challenges for modeling and simulation

Improved automatic differentiation method for efficient model compiler

Model compatibility aspects in multilingual simulation environments

A versatile I/O with robust impedance calibration for various memory interfaces

A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration

An energy-efficient ternary interconnection link for asynchronous systems

Reducing the data switching activity of serialized datastreams

A low power SoC bus with low-leakage and low-swing technique

A 3.0V 12b 120 Msample/s CMOS pipelined ADC

A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm/sup 2/

A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues

Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs

A low voltage, high speed, high resolution class AB switched current sample and hold

A CMOS fifth-order low-pass current-mode filter using a linear transconductor

Fully reconfigurable active-Gm-RC biquadratic cells for software defined radio applications

Transmission line based FIR structures for high speed adaptive equalization

A 10-MHz channel-select filter for a multicarrier WCDMA base-station

A design strategy for VHF filters with digital programmability

Two-dimensional angle and polarization estimation using ESPRIT without pairing

Innovations approach to MMSE waterfilling based equalizers

Estimation of current density distributions from EEG/MEG data by maximizing sparseness of spatial difference

Taylor-series technique for moving source localization in the presence of sensor location errors

Coefficient bias in constant modulus adaptive filters

ETHFB: a new class of even-length wavelet filters for Hilbert pair design

On the regularity of orthonormal wavelets designed via the zero-pinning technique

Improved reversible integer transform

An efficient algorithm for the computation of the reverse jacket transform

A multistandard FFT processor for wireless system-on-chip implementations

The global Lanczos method for MIMO interconnect order reductions

MIMO interconnects order reductions by using the global Arnoldi algorithm

Parametric compact models by directional moment matching

Timing-constrained yield-driven wire sizing for critical area minimization

Memory-based crosstalk canceling CODECs for on-chip buses

An artificial synapse for interfacing to biological neurons

An optical and potential dual-image CMOS sensor for on-chip neural and DNA imaging applications

A wideband power-efficient inductive wireless link for implantable microelectronic devices using multiple carriers

Hybrid silicon/silicone (polydimethylsiloxane) microsystem for cell culture

A low power battery management system for rechargeable wireless implantable electronics

Precoded V-BLAST for ISI MIMO channels

Relaxed tree search MIMO signal detection algorithm design and VLSI implementation

K-best MIMO detection VLSI architectures achieving up to 424 Mbps

Efficient probabilistic sphere decoding architecture

Improved k-best sphere decoding algorithms for MIMO systems

Low power readout control circuit for high resolution CMOS image sensor

A novel neural network-based linearization and auto-compensation technique for sensors

Detection of on-chip temperature gradient using a 1.5V low power CMOS temperature sensor

High SNR capacitive sensing transducer

A hand-held neutron detection sensor system

A technique to design high entropy chaos-based true random bit generators

Chaotic p-ary sequences with exponential auto-correlation properties based on piecewise linear maps

Belief propagation decoding for codes based on discretized chaotic maps

Improving PA efficiency by chaos-based spreading in multicarrier DS-CDMA systems

Phase sampling: a new approach to the design of LF direct digital frequency synthesizers

Measuring harmonics by an improved FFT-based algorithm with considering frequency variations

Prediction of power equipment failures based on chronological failure records

Unit substation demand estimator

Power system network topology identification with MLD transform and tabu search

Radial distribution power flow studies in a remotely distributed environment

Spike timing dependent adaptation for mismatch compensation

An aVLSI recurrent network of spiking neurons with reconfigurable and plastic synapses

Power aware learning for class AB analogue VLSI neural network

Modeling orientation selectivity using a neuromorphic multi-chip system

Sensor compensation using analogue-digital adaptive circuits

A new look at reversible memory elements

Techniques for robust energy efficient subthreshold domino CMOS circuits

Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range

Body-bias regulator for ultra low power multifunction CMOS gates

A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs

Analysis and design of MCML gates with hysteresis

Design considerations for digital circuits using organic thin film transistors on a flexible substrate

A sequence independent power-on-reset circuit for multi-voltage systems

Reducing error accumulation effect in multithreaded memory systems

On the behaviour of passive guard-rings in lightly doped substrates

DCim++: a C++ library for object oriented hardware design and distributed simulation

Passive reduced-order macromodeling algorithm for structure dynamics in MEMS systems

Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method

Energy-efficient scheduling on multi-context FPGAs

Fast word-level power models for synthesis of FPGA-based arithmetic

Simulation of the nano electronic single-electron transistor and the nanoelectronic C-NOT single-electron gate

Logic optimization for majority gate-based nanoelectronic circuits

A simplicial CNN visual processor in 3D SOI-CMOS

Stacked, standing wave detectors in 3D SOI-CMOS

Chip-scale magnetic sensing and control of nanoparticles and nanorods

Retransmission-based error spreading for layered video streaming over wireless LANs

VBR video delivery under constrained resources using motion-aware optimal frame selection

On deployment of overlay network for live video streaming

Improved frame and basic unit layers bit allocation scheme for H.264 video transmission over ARQ-based wireless channels

Error concealment protection for loss resilient bitplane-coded video communications

A novel system for intrabody communication: touch-and-play

Wide-band CMOS low noise amplifier for applications in radio astronomy

Nondestructive durian maturity determination by using microwave free space measurement

A novel pseudorandom binary sequence generator for keystream generation

Optimal distance estimation for the spectral efficiency of an hybrid cellular DS/SFH CDMA system

Weighted Viterbi decoding for MIMO-OFDM systems with linear precoding

A 30GHz 155Mbit/s self-calibrating direct transmitter

Exact BER of transmitter antenna selection/receiver-MRC over spatially correlated Nakagami-fading channels

Linearly precoded ST-OFDM systems in the presence of ISI

The effect of D/A accuracy on the performance of digital predistortion for RF power amplifiers

Fourier series analysis of the nonlinearities in analog closed-loop PWM class D amplifiers

Modeling and analysis of PSRR in analog PWM class D amplifiers

Effect of nonlinearity in the CMFB circuit that uses the differential-difference amplifier

PSRR improvement technique for amplifiers with Miller capacitor

Exploiting circuit instability to achieve wideband linear amplification

A 12-bit 300 MHz CMOS DAC for high-speed system applications

A current copying structure for current-mode monotonic digital-to-analog converters

A low-noise microsensor amplifier with automatic gain control system

A binary-to-thermometer decoder with built-in redundancy for improved DAC yield

A readout circuit for capacitive biosensors with integrated SAR A/D conversion

Data hiding for digital video with phase of motion vector

Generalized lossless data hiding by multiple predictors

A new construction algorithm of visual crytography for gray level images

An improved scalar quantization-based digital video watermarking scheme for H.264/AVC

H.264 native video watermarking method

Multilevel flash memory on-chip error correction based on trellis coded modulation

An efficient test vector compression technique based on block merging

Concurrent error detection in Reed Solomon decoders

Debug support for embedded processor reuse

An on-chip combinational decompressor for reducing test data volume

Analog circuit synthesis: a search for the Holy Grail?

Hierarchical exploration and selection of transistor-topologies for analog circuit design

Supporting analog synthesis by abstracting circuit behavior using a modeling methodology

Architecture refinements by code refactoring of behavioral VHDL-AMS models

Fast evaluation of analog circuit structures by polytopal approximations

Bit level architectural exploration technique for the design of low power multipliers

Segmentation based design of serial parallel multipliers

Post-layout energy-delay analysis of parallel multipliers

A low-power clock frequency multiplier

New viewpoint of bit-serial/parallel normal basis multipliers using irreducible all-one polynomial

Digital post-correction of front-end track-and-hold circuits in ADCs

A nanowatt ADC for ultra low power applications

An ultra-low power silicon-on-sapphire ADC for energy-scavenging sensors

12-bit non-calibrating noise-immune redundant SAR ADC for system-on-a-chip

Implementation of an asynchronous current-mode ADC with adaptive quantization

Realisation of asymmetrical complex filters in log-domain

The approximation of arbitrary complex filter responses

Design of current-mode resonator for wireless applications

Improved building blocks for log-domain linear transformation filters

Compact power-efficient CMOS exponential voltage-to-voltage converter

A low-voltage CMOS linear transconductor suitable for analog multiplier application

A new bulk-driven input stage design for sub 1-volt CMOS op-amps

1.5-V 900-/spl mu/W 40-dB CMOS variable gain amplifier

1.8 V-100 MHz CMOS programmable gain amplifier

A 0.5V fully differential OTA with local common feedback

Robust channel estimation and multiuser detection for MC-CDMA systems under narrowband interference

Transmit/receive beamformer design and power control in MIMO MC-CDMA systems

Optimized QPSK modulator for DVB-S applications

A frequency domain based TEQ design for DSL systems

Intersymbol and intercarrier interference canceller for multi-carrier modulation receivers

A broadcast-based test scheme for reducing test size and application time

Integrating observability don't cares in all-solution SAT solvers

Self-sampled vernier delay line for built-in clock jitter measurement

Phase shifts and linear dependencies

A portable specification of zero-overhead looping control hardware applied to embedded processors

On the wavelet-based elimination of stimulus artifacts in click-evoked otoacoustic emissions

ECG compression using multiscale recurrent patterns with period normalization

Lossless multi-channel EEG compression

Signal processing for brain-computer interface: enhance feature extraction and classification

A new Kalman filter-based power spectral density estimation for nonstationary pressure signals

Low power high linearity transmitter front-end for 900 MHz Zigbee applications

Circuit for statistical estimation of BER and SNR in telecommunications

Compensation of track and hold frequency response mismatches in interleaved analog to digital converters for high-speed communications

A novel loss compensation technique for broadband CMOS distributed amplifiers

Low-voltage, low-power CMOS operation transconductance amplifier with rail-to-rail differential input range

Spectral response improvement of CMOS APS pixel through lateral collection

CMOS pixel-level ADC with change detection

A CMOS image sensor for low light applications

Retinomorphic system design in three dimensional SOI-CMOS

A 100dB dynamic range high-speed dual-line optical transient sensor with asynchronous readout

Quadrature Van der Pol oscillators using second harmonic coupling

Short periodic orbits and topological entropy for the Chua's circuit

Linear range extension of a phase-frequency-detector with saturated output

Injection-lock dynamics in non-harmonic oscillators

Phase noise in dual inverter-based CMOS ring oscillators

Current-mode instantaneous state setting method and its application to an H-bridge inverter

Static generator model for analog power flow computation

Emulation of power system load dynamic behavior through reconfigurable analog circuits

On the determination of adjusted OPF solutions

Application of two-layered tabu search to optimal allocation of UPFC for maximizing transmission capability

Fast video coding based on Gaussian model of DCT coefficients

High speed decoding of context-based adaptive binary arithmetic codes using most probable symbol prediction

Complexity scalable MPEG-2 to WMV transcoder with adaptive error compensation

GES: a new image quality assessment metric based on energy features in Gabor transform domain

Wavelet-based spatially adaptive method for despeckling SAR images

An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme

Low-power and low-latency cluster topology for local traffic NoCs

A very high performance address BUS encoder

Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique

Adaptive low-power bus encoding based on weighted code mapping

Integer linear programming method for spatial temporal mapping of the Viterbi decoder

A robust PRML read channel with digital timing recovery for multi-format optical disc

C-based design of a real time speech recognition system

Programmable FIR filter with adder-based computing engine

Low-power implementation of FIR filters within an adaptive reconfigurable architecture

Library of structural analog cell macromodels for design of continuous-time reconfigurable /spl Delta//spl Sigma/ modulators

Power transfer networks at RF frequencies: new design procedures with implementation roadmap

An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits

Exact hierarchical symbolic analysis of large analog networks using a general interconnection template

Efficient passive transmission line macromodeling algorithm using method of characteristics

A multiobjective service restoration method for power distribution systems

A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI

Floorplan-aware decoupling capacitance budgeting on equivalent circuit model

On the two-dimensional orthogonal drawing of series-parallel graphs

Optimal shielding insertion for inductive noise avoidance

Fast adaptive inter-prediction mode decision method for H.264 based on spatial correlation

Fast wavelet packet basis selection for block-partitioning image coding

JPEG-compliant image coding with adaptive pre-/post-filtering

Image compression with structure-aware inpainting

Reducing computations in MPEG2 video decoder

Synchronization of multihop ad hoc networks using connected dominating sets

Increasing the power efficiency of Bloom filters for network string matching

High speed routing lookup IC design for IPv6

On optical CDMA MAC protocols

Network-on-chip quality-of-service through multiprotocol label switching

Musical instrument classification using non-negative matrix factorization algorithms

Localization based audio source separation by sub-band beamforming

A novel hybrid neuro-wavelet system for robust speech recognition

Automatic speaker change detection with the Bayesian information criterion using MPEG-7 features and a fusion scheme

A new speech modeling method: SYMPES

A high speed and high linearity OTA in 1-V power supply voltage

Offset compensation using unbalanced polarization

Low-voltage floating-gate CMOS buffer

Implementation of space-efficient voltage-insensitive capacitances in integrated circuits

High-voltage drive and I/O interfaces in a 0.35-/spl mu/m CMOS process

Reconfiguration of cascade /spl Sigma//spl Delta/ modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers

A 20-MS/s sigma delta modulator for 802.11a applications

A dual-mode low-distortion sigma-delta modulator with relaxing comparator accuracy

Systematic design method for LC bandpass /spl Sigma//spl Delta/ modulators with feedback FIRDACs

A novel 2-GHz band-pass delta modulator dedicated to wireless receivers

A performance-aware IP core design for multimode transform coding using scalable-DA algorithm

Vertex cache of programmable geometry processor for mobile multimedia application

Realization of QoS management using negotiation algorithms for multiprocessor NoC

A bidirectional linear semi-systolic architecture for DCT-domain image resizing processor

Realization and optimization of DSP based H.264 encoder

Scalable delta-sigma modulator readout architecture for array-based sensor system

Compound noise analysis in digital circuits using blind source separation

A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability

A mixed-structure delay locked-loop with wide range and fast locking

A power-efficient architecture for EBCOT tier-1 in JPEG 2000

On-chip and inter-chip networks for modeling large-scale neural systems

An advanced emulated digital retina model on FPGA to implement a real-time test environment

Locust-inspired vision system on chip architecture for collision detection in automotive applications

Need for large local FPGA-accessible memories in the integration of bio-inspired applications into embedded systems

Bio-inspired massively parallel architectures for nanotechnologies

Techniques to address increased dimensionality of ASIC library design

Virtual self-timed blocks for systems-on-chip

Design of STR level converters for SoCs using the multi-island dual-VDD design technique

A cost-effective reconfigurable accelerator for platform-based SOC design

NoC monitoring: impact on the design flow

1.5-V square-root domain first-order filter with multiple operating points

CMOS voltage-mode analog multiplier

A compact direct digital frequency synthesis architecture

Integrated charge sensitive amplifier with pole-zero cancellation circuit for high rates

Novel linearization technique for low-distortion high-swing CMOS switches with improved reliability

The effects of quantizer metastability on the SNR of continuous-time /spl Sigma//spl Delta/ modulators with return-to-zero switched current DAC

The effect of clock jitter on the DR of /spl Sigma//spl Delta/ modulators

Spectral shaping of clock jitter errors for continuous time sigma-delta modulators

A transistor-based clock jitter insensitive DAC architecture

Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter

Minimal circuit and state space realization of generalized 3-D lattice-ladder discrete filters

A flexible and efficient sharp filter bank architecture for variable bandwidth systems

On the design of two-channel 2D nonseparable multiplet perfect reconstruction filter banks

Design of Mth-band FIR filters based on generalized polyphase structure

Design of optimal quincunx filter banks for image coding

Low-complexity hop timing synchronization in frequency hopping systems

Performance comparison of LDPC-coded FBMC and CP-OFDM in beyond 3G context

Low-power hybrid turbo decoding based on reverse calculation

Block precoder-based energy constrained DFE

MMSE-based design of scaled and offset BP-based decoding algorithms on the fast Rayleigh fading channel

Effective capacitance of RLC loads for estimating short-circuit power

An algorithm for calculating correlation coefficients between Elmore interconnect delays

Design methodology for global resonant H-tree clock distribution networks

Zero skew differential clock distribution network

High performance clock routing in X-architecture

Advances in semantic multimedia analysis for personalised content access

Semantic multimedia analysis for content-adaptive video streaming

Fischlar-TRECVid-2004: combined text- and image-based searching of video archives

Adaptive multimedia access: from user needs to semantic personalisation

Creating meaningful multimedia presentations

Modeling and verification of high-speed wired links with Verilog-AMS

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs

A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution

A reconfigurable fully-integrated 0.18-/spl mu/m CMOS feed forward equalizer IC for 10-Gb/sec backplane links

Automatic within-pair-skew compensation for 6.25 Gbps differential links using wide-bandwidth delay units

Driver's drowsiness estimation by combining EEG signal analysis and ICA-based fuzzy neural networks

Wavelet transforms dedicated to compress recorded ENGs from multichannel implants: comparative architectural study

Real-time seizure monitoring and spectral analysis microsystem

A single chip micro-DNA-array system based on CMOS image sensor technology

A portable phonocardiographic fetal heart rate monitor

Finite switching frequency effects in the sliding mode control of the double integrator system

Fast analytical approach to finding steady-state waveforms for power electronics circuits using orthogonal polynomial basis functions

Adaptive sliding mode control using simple adaptive control for SISO nonlinear systems

Symbolic analysis of bifurcations in planar variable structure systems

Modelling and analysis of multicell converters using discrete time models

Design of a class of maximally-flat spatial filters

A sufficient condition for 1D CNNs with antisymmetric templates to perform connected component detection

Full-range cellular neural networks and differential variational inequalities

A new method for matrix description of genetic algorithms

CNN-based algorithm for drusen identification

A low-power bioamplifier with a new active DC rejection scheme

Biomedical microimplants for sensory and motor neuroprostheses

Signal amplification, detection and transmission in a wireless 100-electrode neural recording system

Switched-capacitor based implantable low-power wireless microstimulating systems

Electro-chemical multi-channel integrated neural interface technologies

On-chip bidirectional transceiver

Is more redundancy better for on-chip bus encoding

Design on new tracking circuit of I/O buffer in 0.13-/spl mu/m cell library for mixed-voltage application

Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic

Charge-pump reducing current mismatch in DLLs and PLLs

Energy-optimal dynamic voltage scaling for sporadic tasks

High level spectral-based analysis of power consumption in DSPs systems

Low-power mechanism with power block management

WL-VC SRAM: a low leakage memory circuit for deep sub-micron design

A probabilistic method to determine the minimum leakage vector for combinational designs

An unscented-transform-based filtering algorithm for noisy contaminated chaotic signals

Calculating distortion in active CMOS mixers using Volterra series

Time-sliding suboptimal regulation of bilinear interconnected systems

Optimization for packet routing using chaotic dynamics

Techniques for improving block error rate of LDPC decoders

A generalized study of multiphase parallel resonant inverters for high-power applications

Performance of pn-junction diode lumped models for circuit simulators

Low-voltage self-oscillating class E electronic ballast for fluorescent lamps

Drive voltage optimization controller to improve efficiency

A time domain measurements procedure of piezoelectric transformers equivalent scheme parameters

Implementation and analysis of microwave switch in CMOS-MEMS technology

A second generation time-to-first-spike pixel with asynchronous self power-off

Asynchronous biphasic pulse signal coding and its CMOS realization

A configurable VLSI chip for DC motor control for compact, low-current robotic systems

CMOS integrated MEMS resonator for RF applications

A 2-GHz CMOS variable gain amplifier optimized for low noise

An ultra-low power predistortion-based FHSS transmitter

Design and modeling of on-chip monolithic transformers with patterned ground shield

Analysis and design of lumped-element quadrature couplers with lossy passive elements

Design of a high linearity mixer for direct-conversion base-station receiver

Improved generalized-proportionate stepsize LMS algorithms and performance analysis

Mean square error analysis of RLS algorithm for WSSUS fading channels

An adaptive algorithm for fast identification of FIR systems

A transform-domain G-PrOBE algorithm

Time delay estimation with coupled LMS filters

Linear switched-capacitor circuit theorems

High-performance analog delays: surpassing Bessel-Thomson by Pade-approximated Gaussians

Decomposed piecewise-linear models by hyperplanes unbending

A new steady-state analysis method for RF-IC circuits driven by multi-tone signals

A method for finding the DC solution regions in piecewise-linear networks

20GHz bandwidth digitizer for single shot analysis

Sampled analog architecture for 2-D DCT

A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters

Design of a tunable fully differential GHz range Gm-C lowpass filter in 0.18 /spl mu/ m CMOS for DS-CDMA UWB transceivers

100MHz, 6th order, leap-frog gm-C high Q bandpass filter and on-chip tuning scheme

Frequency-based object orientation and scaling determination

Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications

A real-time vision-interactive guiding system

Design and evaluation of steganography for voice-over-IP

A perceptually optimized watermarking scheme for color visual information

A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier

Efficient computation of fixed polarity arithmetic expansions for ternary functions

Bidirectional conversion to minimum signed-digit representation

A parallel search algorithm for CLNS addition optimization

Algorithmic truncation of minimax polynomial coefficients

UWB for low data rate applications: technology overview and regulatory aspects

The optimal MAC layer for low-power UWB is non-coordinated

Application of fluid time hopping coding to multiple access in ultra wide band sensor networks

Performance analysis of low complexity solutions for UWB low data rate impulse radio

Orthogonal convolutional modulation for UWB impulse radio communications

Mutual inductance between intentional inductors: closed form expressions

A ladder network delay model for coupled interconnects

Mismatch effect analyses in CMOS tapered buffers

An area-efficient, pulse-based interconnect

A compact 190 /spl mu/W PLL for clock control and distribution in ultra-large scale ICs

Mixed-signal thermometer filtering for low-complexity PLLs/DLLs

Linearity test for high resolution DACs using low-accuracy DDEM flash ADCs

Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers

Process tolerant calibration circuit for PLL applications with BIST

A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet

Slew rate induced distortion in switched-resistor integrators

Synthesis of a current source using a formal design methodology

Linear time-varying filter with variable bandwidth

A simple design method of H/sub /spl infin// reduced-order filters for stochastic systems

Nyquist criterion based design of continuous time /spl Sigma//spl Delta/ modulators

FIR filter design with group delay constraint using semidefinite programming

Design of FIR filters with discrete coefficients via sphere relaxation

Formulas to generate efficient piecewise-polynomial implementations of narrowband linear-phase FIR filters

A genetic algorithm approach for fractional delay FIR filters

A second-order cone programming approach for minimax design of 2-D FIR filters with low group delay

A multifeature voiced/unvoiced decision algorithm for noisy speech

An acoustic noise suppression system with reduced musical artifacts

Direct control on modulation spectrum for noise-robust speech recognition and spectral subtraction

A generalized perceptual time-frequency subtraction method for speech enhancement

Single-channel speech enhancement based on frequency domain ALE

Sparse macromodels for parametric networks

Real time operating system modeling in a system level design environment

A cooperative network of reconfigurable stair-climbing robots

Simulation of SOI transistor circuits through non-equilibrium initial condition analysis (NEICA)

A character size optimization technique for throughput enhancement of character projection lithography

Design and integration of a remotely programmable dental monitoring device

A circuit design of ID-code and heartbeat signal processing blocks of a smart RF ID tag for mice

Low-power, implantable sensing system for signal detection from the central or peripheral nervous system

A high data rate QPSK demodulator for inductively powered electronics implants

Wireless esophageal catheter dedicated to respiratory diseases diagnostic

Design of a practical scheme for ultra wideband communication

An innovative receiver architecture for autonomous detection of ultra-wideband signals

DSP engine design for LINC wireless transmitter systems

Silicon implementation of an MMSE-based soft demapper for MIMO-BICM

Per-survivor processing Viterbi decoder for Bluetooth applications

High performance VLSI architecture of fractional motion estimation in H.264 for HDTV

Analysis of scalable architecture for the embedded block coding in JPEG 2000

Towards an H.264/AVC full encoder on chip: an efficient real-time VBSME ASIC chip

Efficient deblocking filter architecture for H.264 video coders

Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC

Traffic congestion analysis in complex networks

Discontinuity-induced bifurcations in TCP/RED communication algorithms

The optimum power conversion efficiency and associated gain of an LC CMOS oscillator

Prediction of traffic in a public safety network

Complex network topologies and synchronization

CNN-based local motion estimation chip for image stabilization processing

Realization of a CNN-driven cockroach-inspired robot

Lifting-based lossless parallel image coding on discrete-time cellular neural networks

On-chip high-speed solver of inverse problems based on quantum-computing principle

Robustness in binary cellular non-linear networks analog VLSI resonate-and-fire neuron

Adaptive rate control for H.264/AVC using Kalman filter

Data partition for wavefront parallelization of H.264 video encoder

Video denoising using vector estimation of wavelet coefficients

A low complexity hardware architecture for motion estimation

Face segmentation in head-and-shoulder video sequences based on facial saliency map

Dependency driven partitioning objects generation for hardware/software partitioning

Low power design of H.264 CAVLC decoder

SystemC models generation based on libraries of templates

Performance improvement of the H.264/AVC deblocking filter using SIMD instructions

Reverse conversion architectures for signed-digit residue number systems

A high speed and energy efficient full adder design using complementary & level restoring carry logic

Power efficient sequential multiplication using pre-computation

A study of floating-point architectures for pipelined RISC processors

Efficient design of modified Booth multipliers for predetermined coefficients

Low-power multiplier with static decision for input manipulation

Bifurcation analysis of a second-order impact model for forest fire prediction through a 1D-map

Bifurcation theory of a class of perturbed mappings

An investigation on the stability of n-D Lur'e systems

Pattern emergence in strange attractors by directions of mappings

A new classification of neuron models for random inputs on bifurcation structures

CMOS zero cross-conduction low-power driver and power MOSFETs for integrated synchronous buck converter

Theoretical and experimental analysis of Dickson charge pump output resistance

A low-ripple voltage tripler

Automatic substrate switching circuit for on-chip adaptive power supply system

High efficiency cross-coupled doubler with no reversion loss

A CMOS monolithic implementation of a nonlinear element for arbitrary 1D map generation

A CMOS monolithic implementation of a nonlinear interconnection module for a corticonic network

Neural network stream processing core (NnSP) for embedded systems

A VLSI spike-driven dynamic synapse which learns only when necessary

A full-differential analog design of an indirect inverse control law based on neural networks

FIR-RAKE receiver for TD-SCDMA mobile terminals

Tunable word length architecture for low power wireless OFDM demodulator

Design of a low power mixed-signal RAKE receiver

FPGA-based transmitter-receiver architecture of an overlapped FFH-CDMA system: design and simulation

A high-speed, low-power interleaved trace-back memory for Viterbi decoder

Robust adaptive infinite impulse response notch filters: a novel state-space approach

Fault tolerant design of signed digit based FIR filters

Delay-dependent stability of 2D state-delayed linear systems

Closed-form design of maximally flat FIR fractional delay filters

Realization of 2D FIR filters using generalized polyphase structure combined with singular-value decomposition

Design techniques for low-voltage fully differential CMOS switched-capacitor amplifiers

A linear transconductor and its application in an analog filter in 120nm CMOS

New compact and power efficient dynamically biased cascode mirrors and telescopic op-amps

A 0.5 V fully differential gate-input operational transconductance amplifier with intrinsic common-mode rejection

A free but efficient class AB two-stage operational amplifier

Fast startup CMOS current references

Fully programmable bias current generator with 24 bit resolution per bias

A self-calibrated bandgap voltage reference with 0.5 ppm//spl deg/C temperature coefficient

Constant transconductance bias circuit with an on-chip resistor

A 3V 110 /spl mu/W 3.1 ppm//spl deg/C curvature-compensated CMOS bandgap reference

Design and implementation of content-adaptive background skipping for wireless video

SNR-based frame-level video bit rate allocation

A new motion-compensated error concealment scheme for MPEG-4 video transmission

An efficient SNR scalability coding framework hybrid open-close loop FGS coding

Efficient memory architecture for JPEG2000 entropy codec

A high-speed low-energy dynamic PLA using an input-isolation scheme

A new high speed dynamic PLA

Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design

LUT-based MPGAs for fast turnaround time conversion flow

Resource constrained modulo scheduling for coarse-grained reconfigurable arrays

Enhancing power analysis attacks against cryptographic devices

Side channel analysis resistant design flow

Implementation aspects of the DPA-resistant logic style MDPL

An NLFSR-based stream cipher

Elliptic curves cryptosystem implementation based on a look-up table sharing scheme

A power planning model for implantable stimulators

Estimation of the weighted maximum switching activity in combinational CMOS circuits

A charge based computation system and control strategy for energy harvesting applications

Effective tunneling capacitance: a new metric to quantify transient gate leakage current

42% power savings through glitch-reducing clocking strategy in a hearing aid application

Analog circuit sizing with dynamic search window

A mathematical framework for active circuits based on port equivalence using limit variables

A fast state-space algorithm to estimate harmonic distortion in fully differential weakly nonlinear G/sub m/-C filters

Robust analog circuit design: a set theoretic approach

A tool for design exploration and power optimization of CMOS RF circuits blocks

A multibit continuous time sigma delta modulator with successive-approximation quantizer

Quadrature mismatch shaping with a complex, tree structured DAC

Second order dynamic element matching technique for low oversampling delta sigma ADC

A hardware efficient 3-bit second-order dynamic element matching circuit clocked at 300MHz

Digital scheme for quantizer and integrator swing reduction in multibit sigma-delta modulator

Basis picking for matching pursuits audio compression

An architecture for best-basis algorithm using threshold cost function for images

Reconstruction of two-periodic nonuniformly sampled signals using polynomial impulse response time-varying FIR filters

On the design of CMFB transceivers for unknown channels

Concurrent data transmission through PSTN by CDMA

Fast mode decision for spatial scalable video coding

Improved content adaptive update weight control in motion-compensated temporal filtering

Two-dimensional channel rate allocation for SVC over error-prone channel

In-scale motion aligned temporal filtering

Accurately weighting subbands in temporal wavelet transform

Statistical circuit performance variability minimization under manufacturing variations

Characterization of total chip leakage using inverse (reciprocal) gamma distribution

Power-oriented delay budgeting for combinational circuits

Efficient don't care computation for hierarchical designs

Performance-driven crosstalk elimination at post-compiler level

Band-stop noise modulated bandpass sigma-delta analog-to-digital converter

A multiband CMOS RF front-end for 4G WiMAX and WLAN applications

A 5 GHz dual-mode WiMAX/WLAN direct-conversion receiver

A quad-band receiver for GSM/GPRS/EDGE in 90 nm digital CMOS

An OPLL-DDS based frequency synthesizer for DCS-1800 receiver

Design of a CMOS low-voltage low-power circuit for an integrated pulsed ultrasonic distance measurement system

1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-/spl mu/m CMOS

A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique

A CMOS distributed amplifier with current reuse optimization

An adaptive frequency synthesizer architecture reducing reference sidebands

Unequal authenticity protection (UAP) for rate-distortion-optimized secure streaming of multimedia over wireless networks

Adding selective enhancement in scalable video coding for region-of-interest functionality

Network condition detection for video transport over wireless Internet

Upfront intra-refresh decision for low-complexity wireless video telephony

Index assignment design for three-description lattice vector quantization

Absolute stabilization of discrete-time systems with a sector bounded nonlinearity under control saturations

An improved PDS calculation procedure for hybrid systems

A/D and D/A converters by spike-interval modulation of simple spiking neurons

Gaussian chip shaping enhances the superiority of Markovian codes in DS/CDMA systems

A high-speed computational method of fuzzy inference system for embedded systems

Impact of parasitic elements on CMOS charge pumps: a numerical analysis

Integrated low-ripple-voltage fast-response switched-capacitor power converter with interleaving regulation scheme

Integration of class DE inverter for on-chip DC-DC power supplies

Effects of switching power converter nonidealities in envelope elimination and restoration technique

Predicting fast-scale instabilities in switching power converters: a ripple-based unified perspective

An arbitrary kernel convolution AER-transceiver chip for real-time image filtering

Poisson AER generator: inter-spike-intervals analysis

Minimum mean squared error time series classification using an echo state network prediction model

A floating-gate programmable array of silicon neurons for central pattern generating networks

PCI-AER interface for neuro-inspired spiking systems

A portable all-digital pulsewidth control loop for SOC applications

A novel ternary more, less and equality circuit using recharged semi-floating gate devices

Low power and high performance clock delayed domino logic using saturated keeper

High-speed CRC design for 10 Gbps applications

A low-energy low-voltage asynchronous 8051 microcontroller core

Combined image signal processing for CMOS image sensors

A parameterizable digital-approximated 2D Gaussian smoothing filter for edge detection in noisy image

A low-power geometric mapping co-processor for high-speed graphics application

System on chip FPGA designs of a parameterized particle image velocimetry algorithm

Automatic generation of neural networks for image processing

A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process

Feedforward compensation technique for all digital phase locked loop based synthesizers

2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing

Phase locked loop robustness improvement using non integer order loop filter

A modeling platform for efficient characterization of phase-locked loop /spl Delta/-/spl Sigma/ frequency synthesizers

Power minimization of a 433-MHz LC VCO for an implantable neural recording system

A technique to suppress tail current flicker noise in CMOS LC VCOs

A power-optimized CMOS LC VCO with wide tuning range in 0.5-V supply

A 5.3GHz low-phase-noise LC VCO with harmonic filtering resistor

A fully-differential CMOS Clapp VCO for IEEE 802.11a applications

Assessment of probability density estimation methods: Parzen window and finite Gaussian mixtures

A study of complete stability for delayed cellular neural networks

AER tools for communications and debugging

Synchronization and phase synthesis using PLL neural networks

M-SVC (mixed-norm SVC) - a novel form of support vector classifier

A Gb/s one-fourth-rate CMOS CDR circuit without external reference clock

Encoder architecture with throughput over 10 Gbit/sec for quasi-cyclic LDPC codes

A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications

A chaos-based pseudo random number generator using timing-based reseeding method

A 1/4 rate linear phase detector for PLL-based CDR circuits

Spectrum filtering with FRM for robust speech recognition

A Genetic Algorithm for the Design and Optimization of FRM Digital Filters Over a Canonical Double-Base Multiplier Coefficient Space

Application of frequency-response masking technique to the design of a novel modified-DFT filter bank

Complexity reduction for frequency-response masking filters using cyclotomic polynomial prefilters

Fixed-point configurable hardware components for adaptive filters

A threshold voltage variation cancellation technique for analogue peripheral circuits of a display array using poly-Si TFTs

Distributed filter design on silicon CMOS

A universal common-source and common-drain model for 1-20GHz frequency range

Mixed-signal implementation of a nonlinear decoder for delta-sigma encoded stream

A termination technique for the averaging network of flash ADC's

Analytical synthesis of the digitally programmable voltage-mode OTA-C universal biquad

Analytical synthesis of current-mode even-Nth-order single-ended-input OTA and equal-capacitor elliptic filter structure with the minimum components

Electronically controllable biquads using single CDBA

Low-voltage CMOS syllabic-companding log domain filter

A differential 0.13/spl mu/m CMOS active inductor for high-frequency phase shifters

A retina stimulator ASIC with 232 electrodes, custom ESD protection and active charge balancing

A single CMOS chip for biocell trapping, levitation, detection and characterization

A 2.6mW 2fps QVGA CMOS one-chip wireless camera with digital image transmission function for capsule endoscopes

A CMOS contact imager for locating individual cells

A 10-/spl mu/W digital signal processor with adaptive-SNR monitoring for a sub-1V digital hearing aid

Weighted-to-residue and residue-to-weighted converters with three-moduli (2/sup n/ - 1, 2/sup n/, 2/sup n/+1) signed-digit architectures

An RNS architecture of an F/sub p/ elliptic curve point multiplier

Faster elliptic curve point multiplication based on a novel greedy base-2,3 method

A fast kernel for unifying GF(p) and GF(2/sup m/) Montgomery multiplications in a scalable pipelined architecture

A modified high-radix scalable Montgomery multiplier

Time-interleaved analog-to-digital converters: status and future directions

Scalable blind calibration of timing skew in high-resolution time-interleaved ADCs

Blind correction of gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter: experimental verification

On-line calibration of offset and gain mismatch in time-interleaved ADC using a sampled-data chaotic bit-stream

Mismatch compensation techniques using random data for time-interleaved A/D converters

Memory reduction ICFO estimation architecture for DVB-T

Reconfigurable CMOS low noise amplifier for self compensation

An approach for analysing and improving fault tolerance in radio architectures

VLSI implementation of a sequential Monte Carlo receiver

An efficient architecture for distributed resampling for high-speed particle filtering

Q locked loop to tune a high-Q high-frequency bandpass filter

A variable-offset phase detector for phased-array applications

A phase-domain 2nd-order continuous time /spl Delta//spl Sigma/-modulator for frequency digitization

Zero-IF VGA with novel offset cancellation

Adaptive bandwidth PLL with compact current mode filter

A CMOS circuit for embedded GHz measurement of digital signal rise time degradation

Observation of high-frequency analog/RF electrical circuit characteristics by on-chip thermal measurements

A high-quality sine-wave oscillator for analog built-in self-testing

Unit resistor characterization for matching-critical circuit design

Reconfigurable analog interface for mixed signal SOC

Set-membership adaptive algorithms based on time-varying error bounds for DS-CDMA systems

Average power sum of the near-end crosstalk couplings after near-end crosstalk cancellation

Signal expression based on equivalence of time resolution and quantization level

Performance bounds on the constant modulus error surface

Lower bounds for the MSE convergence of APA

Reduced resolution residual coding for H.264-based compression system

Recovery of compressed videos using forward and backward anisotropic diffusion

A scalable fast mode decision algorithm for H.264

A novel fast algorithm for intra mode decision in H.264/AVC encoders

Towards rate-distortion tradeoff in real-time color video coding

System for deposition and characterization of polypyrrole/gold bilayer hinges

Exploring carbon nanotubes and NiSi nanowires as on-chip interconnections

Design and implementation of a 1GHz CMOS resonator utilizing surface acoustic wave

MM11 based flash memory cell model including characterization procedure

Design methodology for hardware-efficient fault-tolerant nanoscale circuits

Relaxing RF component requirements in a Weaver architecture by learning and adapting to the environment

A two-stage digital AGC scheme with diversity selection for frame-based OFDM systems

Implementation of digital IQ imbalance compensation in OFDM WLAN receivers

A self-compensation fixed-width booth multiplier and its 128-point FFT applications

SC filter for RF down conversion with wideband image rejection

High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor

Reencoder design for soft-decision decoding of an (255,239) Reed-Solomon code

Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoder

Analysis of error control code use in ultra-low-power wireless sensor networks

Semi-iterative analog turbo decoding

An adaptable foveating vision chip

A CMOS imager with focal plane compression

A CMOS linear voltage/current dual-mode imager

CMOS image sensor with analog gamma correction using nonlinear single-slope ADC

Two-dimensional CMOS image sensor characterization

On the use of joint diagonalization in blind signal processing

An analysis of the CCA approach for blind source separation and its adaptive realization

Underdetermined sparse source separation of convolutive mixtures with observation vector clustering

Robust super-exponential methods for blind deconvolution of MIMO-IIR systems with Gaussian noise

A generalized deterministic algorithm for blind channel identification with filter bank precoders

Expandable hardware for computing cortical feature maps

Circuits for an RF cochlea

Neuronal ion-channel dynamics in silicon

Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing

Effect of mismatch on the reliability of binary-programmable CNNs

A robust continuous-time multi-dithering technique for laser communications using adaptive optics

Stability analysis for Cohen-Grossberg neural networks with time-varying delays

Feature competition in a spike-based winner-take-all VLSI network

3D position sensing using a Hopfield neural network stereo matching algorithm

Competing and accommodating behaviors of peace SOM

IPC-driven energy reduction for low-power design

Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology

Triple-rail MOS current mode logic for high-speed self-timed pipeline applications

Low power low leakage clock gated static pulsed flip-flop

High performance circuit techniques for dynamic OR gates

Mapping DSP applications on processor/coarse-grain reconfigurable array architectures

Superpipelined reconfigurable hardware for DSP

Binary LNS-based naive Bayes hardware classifier for spam control

A stream register file unit for reconfigurable processors

Efficient architecture for Reed Solomon block turbo code

Analysis of a circuit exhibiting ferroresonance

Adaptive combined bispectrum-filtering signal processing in radar systems with low SNR

A new Spice-oriented frequency-domain optimization technique

Higher order convergent algorithms with applications to polynomials and matrices

Switch synchronizing delayed feedback control for piecewise linear systems

Two-layered neighborhood tabu search for multi-objective distribution network expansion planning

Digital phase-shift modulation for an isolation buffer in silicon-on-sapphire CMOS

Load flow based distribution system short-circuit algorithm incorporating distributed synchronous generators

Photovoltaic inverters with Perturb&Observe MPPT technique and one-cycle control

An adaptive maximum power point tracker for maximising solar cell efficiency in wireless sensor nodes

Very fast programmable CNN based on FG-inverter

A massively parallel algorithm for local binary pattern based face recognition

Optical sensor integrated CNN for real-time computational applications

Fast timing analysis of plane circuits via two-layer CNN-based modeling

On the topographic equivalence between voltage mode and current mode ranked order filters for array processors

Low-power Q-enhancement for parallel LC tanks

Investigation of inductors for digital Si-CMOS technologies

Low-voltage high-linear and isolation transformer based mixer for direct conversion receiver

A 0.13/spl mu/m CMOS T/R switch design for ultrawideband wireless applications

A CMOS down-conversion micromixer for IEEE 802.11b WLAN transceivers

Population fitness probability for effectively terminating the evolution operations of a genetic algorithm

On randomization of digital delta-sigma modulators with DC inputs

Fractional discrete-time chaotic map

A new look at parameter estimation of autoregressive signals from noisy observations

Phase-tracking loop based on delta-sigma oversampling architecture

Balanced 3-phase analog signal processing for radio communications

Noise analysis of continuous-time /spl Sigma//spl Delta/ modulators with switched-capacitor feedback DAC

A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits

Analysis of DC-DC converters containing a transformer

Amplitude modulation based on time-varying forced function of second-order oscillator circuit

Current controlled CDBAs (CCCDBAs)-based novel current-mode universal biquadratic filter

A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system

A 4MHz Gm-C filter with on-chip frequency automatic tuning

A low-voltage, analog power-law function generator

Improving the stability of on-chip automatic tuning loops for continuous-time filters with an analog adaptive controller

An efficient adaptive interlace-to-progressive scan conversion scheme and hardware implementation

Scalable high-throughput architecture for H.264/AVC variable block size motion estimation

An efficient texture cache for programmable vertex shaders

A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications

A bit-serial implementation of mode decision algorithm for AVC encoders

Leakage energy reduction techniques in deep submicron cache memories: a comparative study

Fine grained multi-threshold CMOS for enhanced leakage reduction

Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies

Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies

Nanometer MCML gates: models and design considerations

JPEG2000 image coding system theory and applications

JPWL - an extension of JPEG 2000 for wireless imaging

JPEG2000. Part 10. Volumetric data encoding

JPEG2000 for digital cinema

The emerging JPEG-2000 security (JPSEC) standard

Phase measurement and adjustment of digital signals using random sampling technique

DF-DICE: a scalable solution for soft error tolerant circuit design

High fan-in differential current mirror logic

An improved SAR controller for DLL applications

NIUGAP: low latency network interface architecture with Gray code for networks-on-chip

High-Q CMOS LC pseudo switched-capacitor bandpass filter with center frequency tuning

Process-insensitive modulated-clock voltage comparator

New improved CMOS class AB buffers based on differential flipped voltage followers

Ultra-low-power flash memory in standard 0.35 /spl mu/m CMOS for passive microwave RFID transponders

A register controlled delay locked loop using a TDC and a new fine delay line scheme

On flash A/D-converters with low-precision comparators

Low-power 6-bit flash ADC for high-speed data converters architectures

A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator

A 6-bit low-power compact flash ADC using current-mode threshold logic gates

A 1.5 V high folding rate current-mode folding amplifier for folding and interpolating ADC

Time domain equalization for OFDM systems

Peak-to-average power-ratio reduction for OFDM systems based on method of conditional probability and coordinate descent optimization

Performance of time-frequency localized and frequency selective filter banks in multicarrier systems

The design of a multi-mode/multi-system capable software radio receiver

Subspace based blind channel estimation for space time block coded OFDM system

Fast lossless multi-resolution motion estimation for scalable wavelet video coding

Wavelet domain one-bit transform for low-complexity motion estimation

A fast fractional pel motion estimation algorithm for H.264/MPEG-4 AVC

New results on exhaustive search algorithm for motion estimation using adaptive partial distortion search and successive elimination algorithm

An adaptive search algorithm based on block classification for fast block motion estimation

Use of granular method to design centering

Spice-oriented iterative technique for distortion analysis

A model-based hybrid evolutionary algorithm for fast yield-inclusive design space exploration of analog circuits

Methods for estimating decoupling capacitance of nonswitching circuit blocks

A new approach to the computation of reduced order models for one-port and two-port RC circuits

Energy circulation quadrature LC-VCO

An infinite-skew tolerant delay locked loop

A transformer-based low phase noise and widely tuned CMOS quadrature VCO

Low power LC-VCO design using direct cross-coupled cell biasing

1-V ultra-low-power CMOS LC VCO for UHF quadrature signal generation

A new current-mode incremental signaling scheme with applications to Gb/s parallel links

A new area-efficient 4-PAM 10 Gb/s CMOS serial link transmitter

The extended Kalman filtering algorithm for carrier synchronization and the implementation

Architecture of a hypertransport tunnel

Reconfigurable crossbar switch architecture for network processors

Detecting filopodia with wavelets

A psychiatric patients tracking system

An integrated patch-clamp amplifier in silicon-on-sapphire CMOS

A systolic array technique for determining common approximate substrings

Sleep condition inferencing using simple multimodality sensors

Simulation techniques for noise-analysis in the PLL design process

Locking range analysis for injection-locked frequency dividers

Limit cycles in bang-bang phase-locked loops

Quantization noise reduction using multiphase PLLs

A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time

Messaging and spectrum sharing between ad-hoc cognitive radio networks

A wideband analog multi-resolution spectrum sensing (MRSS) technique for cognitive radio (CR) systems

Multi-band OFDM: a cognitive radio for UWB

Design of a MIMO OFDM baseband transceiver for cognitive radio system

Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems

A low power merge cell processor for real-time spike sorting in implantable neural prostheses

Integrated electrochemical neurosensors

A field programmable neural array

Toward 1000-ch electrode array based on distributed microchip architecture for retinal prosthesis

A neural recording system for monitoring shark behavior

A 4-Kb low power 4-T SRAM design with negative word-line gate drive

Ultra-low power 90nm 6T SRAM cell for wireless sensor network applications

Characterization of a metastability measurement system

Soft error hardening for logic-level designs

A 1.8V p(seudo)SRAM using standard 140nm DRAM technology with self adapting clocked standby operation

EM-based analytical model for estimation of worst-case crosstalk noise

Estimation of supply current spectrum for early noise evaluation

A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects

Wave propagation based analytical model for distributed on-chip RLC interconnects

Network-on-chip link analysis under power and performance constraints

The new improved pseudo fractional-N clock generator with 50% duty cycle

An improved frequency and phase synthesis architecture

1-99% input duty 50% output duty cycle corrector

Modeling the effect of distortion on the phase noise in electrical oscillators

Experimental validation of the bifurcation analysis of a hysteresis oscillator

HOS based minimal transmit redundancy space-time FIR precoder-blind equalizer

Eigenvector algorithms using reference signals for blind source separation of instantaneous mixtures

Blind adaptive equalizer for IIR channels with common zeros

Blind source extraction of instantaneous noisy mixtures using a linear predictor

An efficient algorithm for blind separation of multiple independent sources

Neuromimetic ICs and system for parameters extraction in biological neuron models

Switched pseudo floating-gate reconfigurable linear threshold elements

Differential and geometric properties of Rayleigh quotients with applications

Using self-organizing maps to control physical robots with omnidirectional drives

Nonylphenol biodegradation kinetics estimation using neural networks

A wide band CMOS RF power detector

A reconfigurable, multi-gigahertz pulse shaping circuit based on distributed transversal filters

LNA design for on-chip RF test

Enhanced gm3 cancellation for linearity improvement in CMOS LNAs

An interleaver implementation for the serially concatenated pulse-position modulation decoder

A new QR-decomposition based recursive frequency estimator for multiple sinusoids in impulsive noise environment

A new recursive algorithm for estimating the adaptive function coefficients autoregressive (AFAR) models in impulsive noise environment

Testing a polynomial for zeros inside the unit-circle over the ring of Gaussian integers

Impulse noise detector using mathematical morphology

A two-stage genetic algorithm for the design and optimization of resonator/integrator based sigma-delta A/D and D/A converters

High-voltage operational amplifier based on dual floating-gate transistors

A tunable floating gate CMOS resistor for low-power and low-voltage applications

On-chip current flattening circuit with dynamic voltage scaling

Compact implementation of linear weighted CMOS transconductance adder based on the flipped voltage follower

Broadband capacitive sensor CMOS interface circuit for dielectric spectroscopy

Realization of a low-voltage and low-power Colpitts quadrature oscillator

On an implementation of differential and quadrature Colpitts injection-locked frequency dividers

Synchronization of mutually coupled LC-oscillators

Analog baseband channel for GSM/UMTS/WLAN/Bluetooth reconfigurable multistandard terminals

A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications

A binarization method for scanned documents based on hidden Markov model

Improving the coding of regions of interest

Multiresolution-based texture adaptive motion detection for de-interlacing

Content-based video copy detection with video signature

A novel Fisher discriminant for biometrics recognition: 2DPCA plus 2DFLD

Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop

Low power reference voltages for stepwise display drivers

Low-energy pixel approximation for DVI-based LCD interfaces

Capacitance selection for digital floating-gate circuits operating in subthreshold

Power consumption of a Hamming distance search CAM using neuron MOS transistors

Dynamic control of spinal locomotion circuits

Development of protein chips based on self-assembled monolayer and protein A

Design considerations and recent advances in CMOS-based microsystems for point-of-care clinical diagnostics

Designing synthetic biological networks

CMOS thermal sensing system with simplified circuits and high accuracy for biomedical application

An embedded low power reconfigurable fabric for finite state machine operations

FleXilicon: a reconfigurable architecture for multimedia and wireless communications

CRISP: coarse-grain reconfigurable image signal processor for digital still cameras

A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications

Fine-grain thermal profiling and sensor insertion for FPGAs

A 3 /spl mu/W, 2 MHz CMOS frequency reference for capacitive sensor applications

Wide-range integrated gas sensor interface based on a resistance-to-number converter technique with the oscillator decoupled from the input device

Temperature and flow velocity control for quartz crystal microbalances

A CMOS front-end circuit for integrated fluxgate magnetic sensors

Algorithmic /spl Delta//spl Sigma/-modulated FIR filter

A 110dB dynamic range continuous-time IF-to-baseband /spl Sigma//spl Delta/ modulator for AM/FM/IBOC receivers

A continuous-time band-pass /spl Sigma//spl Delta/ modulator implemented in 0.35/spl mu/m BiCMOS using transmission lines

A 7.5mW, 11-bit continuous-time sigma-delta A/D converter for WLAN applications

A low power 1.1 MHz CMOS continuous-time delta-sigma modulator with active-passive loop filters

Undersampled LC bandpass /spl Sigma//spl Delta/ modulators with feedback FIRDACs

An argument-principle based stability criterion and application to the design of IIR digital filters

Design of IIR all-pass equalizers based on minimum of waveform distortion

Design of half sample delay IIR filter using continued fraction expansion

Design of IIR integrators using Newton-Cotes quadrature rule and fractional sample delay

Digital filter bank design using simple subfilters

Multi-pass algorithm of motion estimation in video encoding for generic GPU

Model-based optimal rate control algorithm for real-time hybrid video encoder

Mode refinement algorithm for H.264 intra frame requantization

An error concealment scheme for entire frame losses based on H.264/AVC

An Address-Event Image Sensor Network

Theory of placement by numDAG related with single-sequence, SP, BSG, and O-tree

Structural analysis of Petri nets with batch processing arcs

Optimal adaptive diagnosis with spares

An improved heuristic algorithm FEIDEQ for the maximum legal firing sequence problem of Petri nets

Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems

A sub-mA, high-gain CMOS low-noise amplifier for 2.4 GHz applications

A 1-V UHF low noise amplifier for ultralow-power applications

Post linearization of CMOS LNA using double cascade FETs

A low-voltage CMOS LNA with multiple magnetic feedback for WLAN applications

A fully differential low noise amplifier with real-time channel hopping for ultra-wideband wireless applications

A low-complexity ICI mitigation method for high-speed mobile OFDM systems

A new common subexpression elimination algorithm for implementing low complexity FIR filters in software defined radio receivers

A WCDMA/HSDPA baseband processor

A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application

Evaluation of stride permutation networks

Programmable synaptic weights for an aVLSI network of spiking neurons

Silicon neurons that phase-lock

Dynamic computation in a recurrent network of heterogeneous silicon neurons

A neural model for sonar-based navigation in obstacle fields

Analog VLSI design of an adaptive neuromorphic chip for olfactory systems

Sequential blind extraction of instantaneous mixtures with arbitrary rank

New Riemannian metrics for speeding-up the convergence of over- and underdetermined ICA

Two-stage series-based neural network approach to nonlinear independent component analysis

An IIR architecture for BSS in strong nonlinear convolutive environments

On the performance of TPC-based STBC coded MIMO-OFDM system over IMT2000 channels

Electron counting based high-radix multiplication in single electron tunneling technology

A new multi-valued static random access memory (MVSRAM) with hybrid circuit consisting of single-electron (SE) and MOSFET

Self-latching operation limits for MOBILE circuits

Dark current and noise of 100nm thick silicon on sapphire CMOS lateral PIN photodiodes

Via placement for minimum interconnect delay in three-dimensional (3D) circuits

Scratch detection via temporal coherency analysis and removal using edge priority based interpolation

Concurrent bit-plane coding architecture for EBCOT in JPEG2000

Color reproduction for digital imaging systems

Video noise reduction in the wavelet domain using temporal decorrelation and adaptive thresholding

Design exploration with an application-specific instruction-set processor for ELA deinterlacing

Stego-signature at logic synthesis level for digital design IP protection

Asynchronous MMC based parallel SA schemes for multiobjective standard cell placement

Hardware implementation and comparison of new defuzzification techniques in fuzzy processors

A novel equaliser architecture with dynamic length optimisation

1-d cellular automaton for pseudorandom number generation and its reconfigurable hardware implementation

Yield enhancement by means of evolutionary computation techniques

Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis

Properties and modeling of ground structures for reducing substrate noise coupling in ICs

A tool for automatic design of analog circuits based on gm/I/sub D/ methodology

Inductance extraction for general interconnect structures

A 2.4-GHz auto-calibration frequency synthesizer with on-chip built-in-self-test solution

PLL-less clock multiplier with self-adjusting phase symmetry

Behavioral macromodeling of analog LSI implementation for automobile intake system

New LC oscillator topology in CMOS 0.18/spl mu/m technology

A novel millimeter-wave multi-order LC oscillator

On the initialization of the DNMF algorithm

Integrating edge detector and bilateral noise filter for enhancing color images

Designing image processing pipeline for color imaging systems

Application of genetic programming to edge detector design

Fast encoding method for vector quantization based on sorting elements of codewords to adaptively constructing subvectors

An ultra-low complexity motion estimation algorithm and its implementation of specific processor

Fast global motion estimation based on iteration least-square estimation with sustained symmetrical structure

Performance analysis of a correlation-based optical flow algorithm under noisy environments

Fast mesh-based motion estimation employing an embedded block model

MPEG complexity reduction by scene adaptive motion estimation

LNA-antenna codesign for UWB systems

Design and performance analysis of DS-UWB rake receiver

A high-speed, low-complexity radix-2/sup 4/ FFT processor for MB-OFDM UWB systems

A CFAR synchronization scheme for impulse based UWB receiver

A low power adaptive transmitter architecture for low band UWB applications

Distributed evidence filtering: the recursive case

Multiuser detection based on Grover's algorithm

Particle swarm localization of acoustic sources in the presence of reverberation

Performance analysis of optimum SMI beamformers for spatial interference rejection

Systematic design flow for dynamic data management in visual texture decoder of MPEG-4

A novel structure for the design of 2-1-1 cascaded continuous time delta sigma modulators

A 2-path bandpass sigma-delta modulator utilizing blue-noise path selection

A low power third order delta-sigma modulator for digital audio applications

A low current consumption delta-sigma modulator for body-implanted chip

A 1.2V, 3.5/spl mu/W, 20MS/s, 8-bit comparator with dynamic-biasing preamplifier

A 6-digit CMOS current-mode analog-to-quaternary converter with RSD error correction algorithm

A 10GS/s 2V/sub pp/ emitter follower only track and hold amplifier in SiGe BiCMOS technology

A digitally calibrated R-2R ladder architecture for high performance digital-to-analog converters

Folded-current-steering DAC: an approach to low-voltage high-speed high-resolution D/A converters

A model for the distortion due to switch on-resistance in sample-and-hold circuits

On cDNA microarray spot localization

Interference severity in nerve cuff recordings due to muscle source relative proximity

A novel electronic architecture used to support biomedical photo-acoustic imaging

Low-complexity technique for secure storage and sharing of biomedical images

Silicon neurons that inhibit to synchronize

Low power state-parallel relaxed adaptive Viterbi decoder design and implementation

Efficient path metric access for reducing interconnect overhead in Viterbi decoders

An efficient regular matrix inversion circuit architecture for MIMO processing

Efficient fast interpolation architecture for soft-decision decoding of Reed-Solomon codes

Parallel encoders for low-density parity-check convolutional codes

High-speed hardware architectures for authenticated encryption mode GCM

Algorithm and implementation of signed-binary recoding with asymmetric digit sets for elliptic curve cryptosystems

Flexible hardware architectures for curve-based cryptography

ASIC hardware implementation of the IDEA NXT encryption algorithm

Hardware architecture and trade-offs for generic inversion of one-way functions

A reconfigurable FIR filter design using dynamic partial reconfiguration

Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI

A case-study on multimedia applications for the XiRisc reconfigurable processor

2-level FIFO architecture design for switch fabrics in network-on-chip

A 1.7mW all digital phase-locked loop with new gain generator and low power DCO

Switched-capacitor track-and-hold amplifier with low sensitivity to op-amp imperfections

A pipelined dual-channel switched capacitor programmable gain amplifier

A new structure for capacitor-mismatch-insensitive multiply-by-two amplification

Power-adaptive operational amplifier with positive-feedback self biasing

A non-uniform sampling approach for the reduction of capacitance spread in SC circuits

New matching methodology of low-noise amplifier with ESD protection

MIMO detection in analog VLSI

Bit stream processing for /spl Delta/-/spl Sigma/ FM-to-digital converters

An asynchronous delta-sigma converter implementation

A 2.4GHz low power wireless transceiver analog front-end for endoscopy capsule system

On the equivalence and factorization of multivariate polynomial matrices

Design of a multidimensional split vector-radix decimation-in-frequency FFT algorithm

Circular array based 2D recursive filtering using a spatio-temporal helix transform

Tracking broadband plane waves using 2D adaptive FIR fan filters

Single-chip FPGA architecture for 3D IIR broadband spatio-temporal beam plane-wave filters

Least squares-based lossless image coding with edge-look-ahead

Feature-oriented multiple description image coding

Efficient dictionary design for multiscale recurrent pattern image coding

Embedded image coding using quincunx directional filter bank

Quality-biased rate allocation for compound image coding with block classification

The impact of 3-dimensional integration on the design of arithmetic units

A mixed analog/digital asynchronous processor for cortical computations in 3D SOI-CMOS

3D integrated sensors in silicon-on-sapphire CMOS

Image sensor with general spatial processing in a 3D integrated circuit technology

Microelectromechanical systems in 3D SOI-CMOS: sensing electronics embedded in mechanical structures

A novel LNA-mixer design with on-chip balun

A low-power signal-recycling mixer and baseband amplifier with current reuse

CMOS mixer design with micromachined input matching circuits for wireless applications

Self-calibration of gain and output match in LNAs

Gain mismatch-balanced I/Q down-conversion mixer for UWB

An all-digital /spl Sigma//spl Delta/-frequency discriminator of arbitrary order

Efficient low-power design and implementation of IQ-imbalance compensator using early termination

A novel technique for low-power D/A conversion based on PAPR reduction

CMOS analog iterative decoders using margin propagation circuits

Homodyne dual six-port network analyzer and associated calibration technique for millimeter wave measurements

The VLSI design of de-interlacing with scene change detection

Algorithm and hardware architecture design for weighted prediction in H.264/MPEG-4 AVC

A novel intra-rate estimation method for H.264 rate control

Adaptive tile depth filter for the depth buffer bandwidth minimization in the low power graphics systems

Double change detection method for moving-object segmentation based on clustering

Modeling the effects of BJT base currents on the dynamics of a log-domain filter

Sensitivity analysis of nonlinear circuits using Volterra series

Dependence of LC VCO oscillation frequency on bias current

A quadrature sinusoidal oscillator with phase-preserving linear frequency control and independent static amplitude control

Communication models with distributed transmission rates and buffer sizes

Load adaptive control scheme to improve converter efficiency and performance

Separate type switched-capacitor (SC) AC-DC converter

Randomized carrier PWM with exponential frequency mapping

Switched-capacitor (SC)/switched inductor (SL) structures for getting hybrid step-down Cuk/Sepic/Zeta converters

Considerations on the control design of DC-link based inverters in grid-connected photovoltaic systems

Disposable CMOS passive RFID transponder for patient monitoring

256-channel integrated neural interface and spatio-temporal signal processor

A CMOS instrumentation amplifier for wideband bioimpedance spectroscopy systems

Power, clock, and data recovery in a wireless neural recording device

Neurodynamic interface circuits for a multichannel, wireless sensor IC operating in saltwater

Low complexity block turbo equalization

A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA

A parallel LSI architecture for LDPC decoder improving message-passing schedule

Decoders for low-density parity-check convolutional codes with large memory

Area-efficient parallel decoder architecture for high rate QC-LDPC codes

Towards an optimised VLSI design algorithm for the constant matrix multiplication problem

Computing during supply voltage switching in DVS enabled real-time processors

On the sensitivity of BDDs with respect to path-related objective functions

Circuit sizing method under delay constraint

Efficient output transition time modeling in CMOS gates with ramp/exponential inputs

An improved design approach for LC tank VCOs

Analysis and evaluation of harmonic distortion in the tunnel diode oscillator

A 0.18/spl mu/m CMOS clock and data recovery circuit with extended operation range

A wide-tuning range 1.8 GHz quadrature VCO utilizing coupled ring oscillators

Amplitude detection inside CMOS LC oscillators

An adaptation method for FIR pre-emphasis filter on backplane channel

Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications

An eye detection technique for clock and data recovery applications

A clock recovery circuit for blind equalization multi-Gbps serial data links

A compact low power mixed-signal equalizer for gigabit Ethernet applications

Dynamic cooperative behavior in a coupled-core fluxgate magnetometer

Transversal noise current in split-drain transistors

Static force measurement by piezoelectric sensors

Noise Effects on Performance of Signal Detection in an Analog VLSI Resonate-And Fire Neuron

Effects of charge-based computation non-idealities on CMOS image compression sensors

Online calibration of quadrature low-IF receivers

A 6.57 mW ZigBee transceiver for 868/915 MHz band

A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels

5.2 GHz self-powered lock and roll radio using VCO injection-locking and on-chip antennas

One-dimensional interpolation based channel estimation for mobile DVB-H reception

The wordlength determination problem of linear time invariant systems with multiple outputs - a geometric programming approach

Realization of MIMO linear discrete-time systems with minimum L/sub 2/-sensitivity and no overflow oscillations

A novel approach to L/sub 2/-sensitivity minimization of digital filters subject to L/sub 2/-scaling constraints

A closed form solution to L/sub 2/-sensitivity minimization of second-order state-space digital filters

Approximately linear-phase recursive digital filters with variable magnitude characteristics

Analytic approach to nullor transformations for FET circuit synthesis. Part I. Nullator-norator tree transformations

Analytic approach to nullor transformations for FET circuit synthesis. Part II. Nullator-norator re-pairing and cloning

Analog circuit synthesis using standard EDA tools

ISECAD: an iterative simulation-equation-based opamp-design CAD tool

Optimization of RF circuits by expert system monitored genetic computation

The effect of switch resistance on pipelined ADC MDAC settling time

Digital background calibration of pipeline ADC with open-loop gain stage

Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs

Analysis of dynamic element matching (DEM) in pipelined ADCs

Jitter analysis of general charge sampling amplifiers

Generalized arbitrary resizing for video transcoding

Improved refinement search for H.263 to H.264/AVC transcoding based on the minimum cost tendency search

Rate-distortion optimization for fast hierarchical B-picture transcoding

Error-resilience transcoding using content-aware intra-refresh based on profit tracing

A low complexity H.263 to H.264 transcoder

Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis

Low power scheduling method using multiple supply voltages

Energy-aware optimal workload allocation among the battery-powered devices to maximize the co-operation life time

Finite state machine state assignment for area and power minimization

Power efficient rapid hardware development using CoDel and automated clock gating

SiP integration of intelligent, adaptive, self-sustaining power management solutions for portable applications

A 65MHZ switching rate, two-stage interleaved synchronous buck converter with fully integrated output filter

A low ripple on-chip charge pump for bootstrapping of the noise-sensitive nodes

Bandwidth limits in PWM switching amplifiers

Multimode digital SMPS controller IC for low-power management

Low power and power aware fractional motion estimation of H.264/AVC for mobile applications

A 1280/spl times/720 pixels 30 frames/s H.264/MPEG-4 AVC intra encoder

Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder

Analysis and VLSI architecture of update step in motion-compensated temporal filtering

A flexible transform processor architecture for multi-CODECs (JPEG, MPEG-2, 4 and H.264)

A 19.5mW 1.5V 10-bit pipeline ADC for DVB-H systems in 0.35 /spl mu/m CMOS

A 10-bit pipeline A/D converter without timing signals

A 1-V 12-bit switched-op amp pipelined ADC with power optimization

A 1.8V, 10-bit, 40MS/s MOSFET-only pipeline analog-to-digital converter

A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique

Continuous time delta sigma modulators with reduced clock jitter sensitivity

Clock jitter compensation for current steering DACs

High-pass /spl Delta//spl Sigma/ modulator: from system analysis to circuit design

A low-distortion fourth-order bandpass delta-sigma modulator

A CMOS implementation of time-interleaved high-pass /spl Delta//spl Sigma/ modulator

MMSE equalization for bandwidth-efficient multicarrier systems

An efficient implementation of linear-phase FIR filters for a rational sampling rate conversion

Average rate behavior for cooperative diversity in wireless networks

A new algorithm for optimum bit loading with a general cost

Reduced-order H/sub /spl infin// and H/sub 2/ design of multirate filter banks using PDLF method

Distributed video coding based on adaptive binning

Distributed video coding with 3D recursive search block matching

High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard

Video compression based on orthonormal matching pursuits

Distributed video coding using wavelet

Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells

A congestion-driven buffer planner with space reservation

Multilevel timing-constrained full-chip routing in hierarchical quad-grid model

Routing algorithms: architecture driven rerouting enhancement for FPGAs

Congestion-driven W-shape multilevel full-chip routing framework

Analysis of self mixing of transmitter interference in WCDMA receivers

300-Mbps OFDM baseband transceiver for wireless LAN systems

Fast automatic gain control employing two compensation loop for high throughput MIMO-OFDM receivers

A delay generation technique for fast-locking frequency synthesizers

Low-complexity synchronization technique with adaptive mode detection for DVB-H system

Demonstration of latency reduction in electrical interconnections using optical fanout

A low-voltage supply optoelectronic detector-receiver in a commercial silicon-based process

Common-emitter feedback transimpedance amplifier for analog optical receivers

A 1.8V, 60dB/spl Omega/ 11 GHz transimpedance amplifier with strong immunity to input parasitic capacitance

Inductor-less 10Gb/s CMOS transimpedance amplifier using source-follower regulated cascode and double three-order active feedback

Compressed domain content-based retrieval of MP3 audio example using quantization tree indexing and melody-line tracking method

Texture image retrieval using complex directional filter bank

Co-occurrence features of multi-scale directional filter bank for texture characterization

Complete Kernel Fisher discriminant analysis of Gabor features with fractional power polynomial models for face recognition

Automatic video annotation based on co-adaptation and label correction

Averaging method analysis of a new mutual synchronization method from living organism

An efficient homotopy method that can be easily implemented on SPICE

Performance of chaotic switching noise injected to Hopfield NN for quadratic assignment problem

Complicated superstable behavior in a piecewise constant circuit with impulsive switching

Number of stimulation units needed to derive all the phase patterns in pulse-driven star-coupled LC oscillators

An approach for efficient design of digital amplifiers

A parallel model combination scheme with improved delta parameter compensation

Blind dereverberation using correlation coefficients considering periodicity of voiced speech

A computationally efficient DAB bit-stream processor

A blind identification technique for noisy ARMA systems

Tongue drive: a tongue operated magnetic sensor based wireless assistive technology for people with severe disabilities

A CMOS potentiostat for control of integrated MEMS actuators

Virtual time-variant model of the Eustachian tube

A computer-aided-diagnosis of tonsillitis using tonsil size and color

Markovian level set for echocardiographic image segmentation

Frame-level data reuse for motion-compensated temporal filtering

Multi-object tracking VLSI architecture using image-scan based region growing and feature matching

FPGA-based architecture for real-time IP video and image compression

A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264

Implementation of H.264/AVC decoder for mobile video applications

Floorplanning for 2.5-D system integration using multi-layer-BSG structure

On handling the fixed-outline constraints of floorplanning using less flexibility first principles

A novel technique integrating buffer insertion into timing driven placement

A novel low-power physical design methodology for MTCMOS

Buffer planning based on block exchanging

An integrated countermeasure against differential power analysis for secure smart-cards

Generalized buffering of PTL logic stages using Boolean division

Model of a true random number generator aimed at cryptographic applications

Testable and self-repairable structured logic design

Effects of crosstalk noise on H-tree clock distribution networks

AC-DC converters with bi-directional power flow and some possible applications

Unified motor controller based on space vector modulation technique

QFT control for DC-DC buck converters

A single inductor multiple output converter with adaptive delta current mode control

On the basins of attraction of parallel connected buck switching converters

Design of a MIMO-OFDM baseband receiver for next-generation wireless LAN

Interlaced pilot channel estimation in MIMO-OFDM systems

Performance analysis of the Bayesian beam former on the CDMA reverse channel

An efficient parallelization technique for high throughput FFT-ASIPs

Effects of RF impairments in transmitter for the future beyond-3G communications systems

Practical review of advanced CDMA receivers with emphasis in the downlink

Capacity analysis of adaptive multiuser frequency-time domain radio resource allocation in OFDMA systems

A 0.13 /spl mu/m CMOS delay cell for 40 Gb/s FFE equalization

Performance of a DSSS superregenerative receiver in the presence of noise and interference

Phase noise in bipolar and CMOS VCO's - an analytical comparison

Analysis of signal distortion due to third order nonlinearity in WCDMA receivers

A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver

Adaptive TDTL with enhanced performance using sample sensing technique

Low voltage 2-mW 6/spl sim/10.6-GHz ultra-wideband CMOS mixer with active balun

A 0.18/spl mu/m CMOS 10Gb/s 1:4 DEMUX using replica-bias circuits for optical receiver

Time domain analysis of analog filters in MATLAB/spl reg/ environment

Accurate transient response model for automatic synthesis of high-speed operational amplifiers

Automatic procedure generating noise models for discrete-time applications

Performance and power analysis on asynchronous reading of binary arrays

Radio-triggered solar and RF power scavenging and management for ultra low power wireless medical applications

Band connections in active cancellation circuits against digital substrate noise

Analog frequency response measurement in mixed-signal systems

A single-chip audio system with delta-sigma DAC and class-D amplifier

Analog fault AC dictionary creation - the fuzzy set approach

Built-in self-test mode in a multi-path feedforward compensated operational amplifier

An adaptive CUSUM-based test for signal change detection

A new watermarking system for joint ownership verification

A vector quantizer classifier for blind signal to noise ratio estimation of speech signals

Parametric estimation of nonlinear systems through sequences designed using DNA computation

A generalized signal reconstruction method for designing interpolation filters

2005 IEEE International Symposium on Circuits and Systems

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003.

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

1993 IEEE International Symposium on Circuits and Systems

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

1991., IEEE International Sympoisum on Circuits and Systems

IEEE International Symposium on Circuits and Systems

IEEE International Symposium on Circuits and Systems,

1988., IEEE International Symposium on Circuits and Systems

A power planning model for implantable stimulators

Content Provider	IEEE Xplore Digital Library
Author	Hashemi, S. Sawan, M. Savaria, Y.
Copyright Year	2006
Description	Author affiliation: Ecole Polytechnique de Montreal, Que. (Hashemi, S.; Sawan, M.; Savaria, Y.)
Abstract	This paper presents a new analytical, empirical and behavioral modular model developed for accurate evaluation of power dissipation in power conversion chains (PCC) dedicated to power up an electronic implantable device. The model is suitable for power estimation/planning in early design stages, to determine the contribution of each circuit module on the total power consumption and to estimate the input and output voltages of these modules. It is based on average power consumption model and is coded in Verilog-A. The model is verified and the results were found to be in good agreement with state-of-the-art designs for bioelectronics devices. It is flexible and robust to changes in architecture and design parameters and provides accurate and valid results in a fraction of second for a large variety of parameter values. The ease of implementing desired modules and architectures makes the model more advantageous
Sponsorship	The Inst. of Electr. and Electron. Eng., Inc. Circuits and Syst. Soc. (IEEE CASS)
File Size	1532201
File Format	PDF
ISBN	0780393899
DOI	10.1109/ISCAS.2006.1693237
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-21
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Biological system modeling Circuit simulation Energy consumption Power dissipation Analytical models Voltage Sampling methods Hardware design languages Robustness Combinational circuits
Content Type	Text
Resource Type	Article

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