NDLI: A New Partitioning Scheme of Parallel VHDL Simulation

Content Provider	IEEE Xplore Digital Library
Author	Wu Yue Jian Ling Yang Hong-Bin Liu Zong-Tian
Copyright Year	2005
Description	Author affiliation: Sch. of Comput. Eng. & Sci., Shanghai Univ. (Wu Yue; Jian Ling; Yang Hong-Bin; Liu Zong-Tian)
Abstract	The static partitioning algorithm and assigning were generally researched respectively, which has largely resulted in the deficiency in the workload balance of the static partitioning. A new partitioning scheme of parallel VHDL simulation is presented in the paper. Partitioning and assigning both are processed just before the simulation in the scheme, and are included in the running phase. Because of this, it strictly requests that the time complexity of partitioning algorithm is minimum. A new static partitioning algorithm, fan-out right partitioning algorithm, which has a lower time complexity and good performance, is presented in the paper. The experiment result shows that the performance of parallel VHDL simulation is improved with this scheme and partitioning algorithm
Starting Page	1
Ending Page	4
File Size	90028
Page Count	4
File Format	PDF
ISBN	0780392922
DOI	10.1109/HDP.2005.251452
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Partitioning algorithms Circuit simulation Very large scale integration Algorithm design and analysis Computational modeling Computer simulation Concurrent computing Software algorithms Digital circuits Hardware design languages
Content Type	Text
Resource Type	Article

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