NDLI: Energy efficient design for subthreshold supply voltage operation

Content Provider	IEEE Xplore Digital Library
Author	Blaauw, D. Zhai, B.
Copyright Year	2006
Description	Author affiliation: Michigan Univ., Ann Arbor, MI (Blaauw, D.; Zhai, B.)
Abstract	Subthreshold design has become an important area in low-power design due to its ultra-low power consumption and high energy efficiency. This is very useful in mobile applications where battery life is crucial. For most current DVS processor designs, the voltage range is limited from full $V_{dd}$ to approximately half Vdd at most. Subthreshold design enables wide-range dynamic voltage scaling (DVS) by allowing circuits to operate in subthreshold voltages. In this paper we give an overview of several issues in energy-efficient subthreshold design. First, from a theoretical point of view, we show that, for subthreshold supply-voltages, leakage energy becomes dominant, making "just in time completion" energy inefficient. We derive an analytical model for the minimum energy-optimal voltage and study its trends with technology scaling. Second, we evaluate different low-power approaches such as MTCMOS (multiple-threshold CMOS) and DVS and show that wide-range DVS provides the best energy efficiency. Finally, we study the impact of process variation on subthreshold operation and discuss which sources of process variation are dominant in this regime and how they can be addressed
Sponsorship	The Inst. of Electr. and Electron. Eng., Inc. Circuits and Syst. Soc. (IEEE CASS)
Starting Page	4
Ending Page	32
File Size	4295651
Page Count	29
File Format	PDF
ISBN	0780393899
DOI	10.1109/ISCAS.2006.1692514
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-21
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy efficiency Dynamic voltage scaling Voltage control Inverters Threshold voltage Resource description framework Delay Circuit synthesis Energy consumption Batteries
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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