NDLI: Routing algorithms: architecture driven rerouting enhancement for FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Taghavi, T. Ghiasi, S. Sarrafzadeh, M.
Copyright Year	2006
Description	Author affiliation: Dept. of CS, UCLA, Los Angeles, CA (Taghavi, T.; Ghiasi, S.; Sarrafzadeh, M.)
Abstract	The routing channels of today's FPGAs consist of wire segments of various types, which allow the use of new techniques to enhance the routability of net segments in channels. In this paper we present an optimal greedy algorithm to switch the tracks that net segments are assigned to. This allows us to enhance the rerouting ability by capturing the features of the routing architecture. Suppose the number of tracks in the channels is given. The goal of this algorithm is to increase the number of routed segments of late rerouting requests. This is a good feature for supporting engineering change order (ECO) type of routing. Supporting ECO routing enables the routing algorithms to deal with later changes in routing requests. We used the routing architecture of VirtexII FPGAs from Xilinx as our target architecture and integrated our algorithm into the VPR FPGA routing tool. The experimental results show that our algorithm makes VPR router capable of handling 28.4% more rerouting for segments that are added to the design later
Sponsorship	The Inst. of Electr. and Electron. Eng., Inc. Circuits and Syst. Soc. (IEEE CASS)
Starting Page	4
Ending Page	5446
File Size	4245798
Page Count	5443
File Format	PDF
ISBN	0780393899
DOI	10.1109/ISCAS.2006.1693865
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-21
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Field programmable gate arrays Switches Wire Greedy algorithms Iterative algorithms Algorithm design and analysis Design automation Abstracts Circuits Left Edge Algorithm FPGA CAD Greedy algorithm
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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