NDLI: Predictive Simulation and Benchmarking of Si and Ge pMOS FinFETs for Future CMOS Technology

Content Provider	IEEE Xplore Digital Library
Author	Shifren, L. Aitken, R. Brown, A.R. Chandra, V. Binjie Cheng Riddet, C. Alexander, C.L. Cline, B. Millar, C. Sinha, S. Yeric, G. Asenov, A.
Copyright Year	1963
Abstract	In this paper, we study and compare Si versus Ge pMOS FinFETs at advanced node dimensions using ensemble Monte Carlo simulations. It is found that due to large external resistance, lack of stressing methods, smaller bandgap, larger dielectric constant, and increased variability that in the absence of major innovation, Ge is not an ideal candidate for channel replacement material of pMOS in future CMOS technology generation FinFETs. In order for Ge to compete with Si, it would at a minimum require a stressing mechanism and improved contact resistance, but leakage and variability would still be a concern for low-power applications.
Sponsorship	IEEE Electron Devices Society
Starting Page	2271
Ending Page	2277
Page Count	7
File Size	2349776
File Format	PDF
ISSN	00189383
Volume Number	61
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon FinFETs Resistance Electromagnetic compatibility Contact resistance Substrates Stress SiGe. 7-nm node 10-nm node advanced node process CMOS CMOS variability device physics FinFET germanium MOSFET process technology SiGe
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances

7-nm FinFET CMOS Design Enabled by Stress Engineering Using Si, Ge, and Sn

Analysis of the Performance of n-Type FinFETs With Strained SiGe Channel

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

Comparison of Gate-Metal Work Function Variability Between Ge and Si p-Channel FinFETs

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD- $hbox{SiN}_{x}$ Stressing Layer

A Patterning-Based Strain Engineering for Sub-22 nm Node FinFETs

Ge-Rich (70%) SiGe Nanowire MOSFET Fabricated Using Pattern-Dependent Ge-Condensation Technique

Predictive Simulation and Benchmarking of Si and Ge pMOS FinFETs for Future CMOS Technology

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The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances

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Analysis of the Performance of n-Type FinFETs With Strained SiGe Channel

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

Comparison of Gate-Metal Work Function Variability Between Ge and Si p-Channel FinFETs

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