NDLI: Stochastic Modeling of Positive Bias Temperature Instability in High-<inline-formula> <tex-math notation=TeX>(kappa ) </tex-math></inline-formula> Metal Gate nMOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Hassan, M.K. Chih-Hsiang Ho Roy, K.
Copyright Year	1963
Abstract	Positive bias temperature instability (PBTI) has become one of the major reliability concerns in the present day CMOS technology. The PBTI mostly degrades the performance of high-κ/metal gate (HK/MG) nMOSFETs and is dominated by time dependent stress induced trap generation. The PBTI models proposed so far in different literature are deterministic in nature and overlook the randomness of the temporal degradation of transistor threshold voltage, V_th. In this paper, we present a stochastic model for PBTI to predict the behavior of HK/MG nMOSFETs under inversion mode stress. The model is scalable and is verified against experimental data from two different groups. Our model separately considers each trap to predict their impact on device performance. The simulations are carried out at accelerated voltage and temperature conditions and we noted the variations in V_th. In addition, we have analyzed the impact of PBTI on the performance of a ring oscillator and concluded that the circuit speed suffers significant degradation due to this effect. We have also observed that the adverse effect of PBTI becomes more severe as we go deeper into the nanometer technology.
Sponsorship	IEEE Electron Devices Society
Starting Page	2243
Ending Page	2249
Page Count	7
File Size	2547289
File Format	PDF
ISSN	00189383
Volume Number	61
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Degradation Stress Hafnium compounds Electron traps Dielectrics Transistors Threshold voltage variability. High-κ (HK) positive bias temperature instability (PBTI) reliability trap charging trap generation variability High- \(\kappa \) (HK)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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A Charge-Trapping Model for the Fast Component of Positive Bias Temperature Instability (PBTI) in High- (kappa ) Gate-Stacks

Positive Bias Temperature Instability Effects in nMOSFETs With $hbox{HfO}_{2}/hbox{TiN}$ Gate Stacks

Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-$kappa$ Metal-Gate Devices

Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide

New Insight Into PBTI Evaluation Method for nMOSFETs With Stacked High- $k$/IL Gate Dielectric

PBTI-Associated High-Temperature Hot Carrier Degradation of nMOSFETs With Metal-Gate/High- $k$ Dielectrics

A Fast Four-Point Sense Methodology for Extraction of Circuit-Relevant Degradation Parameters

Electrical observation of deep traps in high-/spl kappa//metal gate stack transistors

Experimental Investigation of Border Trap Generation in InGaAs nMOSFETs With $hbox{Al}_{2}hbox{O}_{3}$ Gate Dielectric Under PBTI Stress

Stochastic Modeling of Positive Bias Temperature Instability in High- (kappa ) Metal Gate nMOSFETs

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