NDLI: Impact of Charge-Trap Layer Conductivity Control on Device Performances of Top-Gate Memory Thin-Film Transistors Using IGZO Channel and ZnO Charge-Trap Layer

Content Provider	IEEE Xplore Digital Library
Author	Jun Yong Bak Min-Ki Ryu Sang Hee Ko Park Chi-Sun Hwang Sung Min Yoon
Copyright Year	1963
Abstract	A top-gate-structured charge-trap-type memory thin-film transistors (CTM-TFTs) using In-Ga-Zn-O (IGZO) channel and ZnO charge-trap layers were proposed to investigate effects of conductivity modulation for charge-trap layers on the memory performances. The electrical conductivity of ZnO charge-trap layers were controlled by varying the deposition temperatures to 100 °C (CTM1), 150 °C (CTM2), and 200 °C (CTM3) during the atomic layer deposition process and this strategy was well confirmed in the controlled devices using the conductivity-modulated ZnO channel layers. The IGZO TFT without charge-trap layer was also evaluated to have excellent device characteristics thanks to the high-quality interface between IGZO and Al₂O₃ tunneling layer. The CTM1 and CMT2 exhibited a wide memory window (MW), sufficiently high program speed, and strong endurance properties. However, these promising memory behaviors could not be obtained for the CTM3 owing to its highly conductive charge-trap layer. For the evaluation of retention properties, there were big difference between the CTM1 and CTM2. Consequently, the CTM1 exhibited best memory performances. The MW and the memory margin in programmed current (ION/OFF) were estimated to be 17.1 V, and 1.3 × 10⁸, respectively. The I_ON/OFF was obtained to be 2.6 × 10⁶ and 1.8 × 10³ after the 10⁴ times cyclic operations and after the retention test for 10⁴ s, respectively.
Sponsorship	IEEE Electron Devices Society
Starting Page	2404
Ending Page	2411
Page Count	8
File Size	1346190
File Format	PDF
ISSN	00189383
Volume Number	61
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Zinc oxide Conductivity Logic gates Thin film transistors Electron traps Temperature Temperature measurement ZnO. Charge-trap layer charge-trap memory (CTM) conductivity oxide semiconductor top-gate structure ZnO
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Nonvolatile Charge-Trap Memory Transistors With Top-Gate Structure Using In–Ga–Zn-O Active Channel and ZnO Charge-Trap Layer

Photo-Stable Transparent Nonvolatile Memory Thin-Film Transistors Using In–Ga–Zn–O Channel and ZnO Charge-Trap Layers

Vertical Channel ZnO Thin-Film Transistors Using an Atomic Layer Deposition Method

Modeling of Self-Aligned Vertical ZnO Thin-Film Transistors

Solution-Processed Zinc Oxide Thin-Film Transistors With a Low-Temperature Polymer Passivation Layer

Transparent IGZO-Based Logic Gates

Low-Frequency Noise Properties in Double-Gate Amorphous InGaZnO Thin-Film Transistors Fabricated by Back-Channel-Etch Method

Oxide Semiconductor Thin Film Transistors on Thin Solution-Cast Flexible Substrates

Charge Trapping Memory Characteristics of Amorphous-Indium–Gallium–Zinc Oxide Thin-Film Transistors With Defect-Engineered Alumina Dielectric

Impact of Charge-Trap Layer Conductivity Control on Device Performances of Top-Gate Memory Thin-Film Transistors Using IGZO Channel and ZnO Charge-Trap Layer

Similar Documents

Nonvolatile Charge-Trap Memory Transistors With Top-Gate Structure Using In–Ga–Zn-O Active Channel and ZnO Charge-Trap Layer

Photo-Stable Transparent Nonvolatile Memory Thin-Film Transistors Using In–Ga–Zn–O Channel and ZnO Charge-Trap Layers

Vertical Channel ZnO Thin-Film Transistors Using an Atomic Layer Deposition Method

Modeling of Self-Aligned Vertical ZnO Thin-Film Transistors

Solution-Processed Zinc Oxide Thin-Film Transistors With a Low-Temperature Polymer Passivation Layer

Transparent IGZO-Based Logic Gates

Low-Frequency Noise Properties in Double-Gate Amorphous InGaZnO Thin-Film Transistors Fabricated by Back-Channel-Etch Method

Oxide Semiconductor Thin Film Transistors on Thin Solution-Cast Flexible Substrates

Charge Trapping Memory Characteristics of Amorphous-Indium–Gallium–Zinc Oxide Thin-Film Transistors With Defect-Engineered Alumina Dielectric

Impact of Charge-Trap Layer Conductivity Control on Device Performances of Top-Gate Memory Thin-Film Transistors Using IGZO Channel and ZnO Charge-Trap Layer