NDLI: Variation resilient reliable design of trigger pulse generator

Content Provider	IET Digital Library
Author	Kumar, Amresh Dwivedi, Amit Krishna Islam, Aminul
Abstract	This study presents a robust design of a trigger pulse generator that produces trigger pulses of variable widths/durations that are tuned using an external control as per the requirements. The proposed design comprises two elementary modules: a delay element and an XOR circuit. The proposed circuit is implemented using a 16 nm CMOS technology node and simulation results have been verified using the SPICE simulator. Various performance parameters such as power consumption, power delay-product, energy-delay product and impact of key circuit parameters [supply voltage (V DD), channel length (Lg), gate width (Wg), channel doping concentration (N A), oxide thickness (T OX), threshold voltage (V T) and carrier mobility (µ o)] on the duration of trigger pulses have been studied in-depth and performance parameters are compared with circuits already available in the literature. The proposed circuit produces trigger pulses of a minimum width of 191.3 ps at a nominal supply of 1.0 V with an average power consumption of 160 nW. The width of the trigger pulses can be varied from 191.3 to 457.2 ps using an external control from 1.0 to 0.7 V, respectively, at 16 nm technology node.
Starting Page	860
Ending Page	868
Page Count	9
ISSN	1751858X
Volume Number	14
e-ISSN	17518598
Issue Number	Issue 6, Sep (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/14/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2019.0362
Journal	IET Circuits, Devices & Systems
Publisher Date	2020-05-26
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Carrier Mobility Channel Doping Concentration Channel Length CMOS Integrated Circuit CMOS Logic Circuit CMOS Technology Node Delay Circuit Delay Element Digital Circuit Design, Modelling And Testing Energy-delay Product Gate Width Integrated Circuit Reliability Logic And Switching Circuit Logic Circuit Logic Design Method Oxide Thickness Power 160.0 NW Power Consumption Power Delay-product Power Electronics Power Supply Pulse Circuit Pulse Generator Reliability Size 16.0 Nm SPICE Simulator Supervisory Circuit Supervisory Control Signal Threshold Voltage Time 191.3 Ps to 457.2 Ps Trigger Circuit Trigger Pulse Generator Variation Resilient Reliable Design Voltage 0.7 V to 1.0 V XOR Circuit
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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