NDLI: Hybrid bidirectional transceiver for multipoint-to-multipoint signalling across on-chip global interconnects

Content Provider	IET Digital Library
Author	Wary, Nijwm Chowdhury, Antroy Roy Mandal, Pradip
Abstract	The authors propose a hybrid transceiver and an energy-efficient link architecture for bidirectional multipoint-to-multipoint signalling across on-chip global interconnect. The proposed link architecture eliminates the need for passive termination for bandwidth enhancement by means of active termination, reducing the required transmitter signalling current drastically and hence, improving the overall energy efficiency of the link. Also, compared to existing passive terminated interconnect with current-mode receivers at all the points, the proposed link deploys low impedance current-mode receivers providing active terminations at both the ends of the interconnect and high-impedance voltage-mode receivers, which do not consume any portion of the signalling current, at the intermediate nodes of the interconnect which further lowers the required transmitter signalling current. A mixed-mode or hybrid transceiver architecture has been proposed for the aforementioned link, which can act either as a current-mode transmitter or a current-mode receiver or a voltage-mode receiver. The architecture has been implemented in 0.18-μm complementary metal oxide semiconductor technology for an interconnect of length 4 mm and having five transceiver nodes. The total energy efficiency of the architecture is 0.70 pJ/b for a speed of 3.0 Gb/s.
Starting Page	780
Ending Page	787
Page Count	8
ISSN	1751858X
Volume Number	14
e-ISSN	17518598
Issue Number	Issue 6, Sep (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/14/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2019.0465
Journal	IET Circuits, Devices & Systems
Publisher Date	2020-04-19
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Active Termination CMOS Digital Integrated Circuit CMOS Integrated Circuit Current-mode Circuit Current-mode Transmitter Electrical/electronic Equipment Energy Conservation Energy Efficiency Energy Utilisation Energy-efficient Link Architecture High-impedance Voltage-mode Receiver Hybrid Bidirectional Transceiver Hybrid Transceiver Architecture Integrated Circuit Interconnections Low Impedance Current-mode Receiver Low Power Electronics Metallisation And Interconnection Technology Mixed-mode Transceiver Architecture Multipoint-to-multipoint Signalling Network-on-chip On-chip Global Interconnect Passive Terminated Interconnect Passive Termination Size 0.18 Mum Size 4.0 Mm Transceiver Node Transceivers Transmitter Signalling Voltage-mode Receiver
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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