NDLI: FPGA and ASIC realisation of EMD algorithm for real-time signal processing

Content Provider	IET Digital Library
Author	Das, Kaushik Nath, Debanjali Pradhan, Sambhu Nath
Abstract	In this study, the authors have proposed both field-programmable gate array (FPGA) and application specific integrated circuit (ASIC) based realisation of the empirical mode decomposition (EMD) algorithm for the real-time signal processing. Here, a single module is used for the calculation of maxima and minima, and another single module is used for the calculation of upper and lower envelopes instead of using separate modules for each calculation. In this work, the traditional cubic spline interpolation has been replaced with sawtooth transform followed by a smoothing module called moving average. In this study firstly, Verilog-HDL code for the EMD is written using Xilinx Vivado and tested in the simulation phase, later dumped into Digilentinc Basys 3 FPGA board to do the hardware verification. For ASIC, the code is synthesised using Cadence Genus tool with the semi-conductor laboratory 180 nm cell library and the layout is made in the Cadence Innovus tool. The proposed EMD can work with a clock/sampling rate up to 25 MHz and has a layout area of 3.9 mm2. For the reduction of power consumption of the overall system, clock gating has been used which helps to reduce the dynamic power of the modules, when they are not in use.
Starting Page	741
Ending Page	749
Page Count	9
ISSN	1751858X
Volume Number	14
e-ISSN	17518598
Issue Number	Issue 6, Sep (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/14/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2019.0322
Journal	IET Circuits, Devices & Systems
Publisher Date	2020-03-10
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Application Specific Integrated Circuit ASIC Cadence Genus Tool Cadence Innovus Tool Clock Gating Digilentinc Basys 3 FPGA Board Digital Circuit Design, Modelling And Testing Digital Signal Processing Dynamic Power Reduction EMD Algorithm Empirical Mode Decomposition Algorithm Field Programmable Gate Array Field-programmable Gate Array Frequency 25.0 MHz Hardware Description Languages Hardware Verification Hilbert Transform Integral Transforms in Numerical Analysis Integrated Circuit Design Interpolation Interpolation And Function Approximation Layout Logic And Switching Circuit Logic Circuit Logic Design Method Mathematics Mathematics Computing Modelling And Testing Moving Average Numerical Analysis Power Consumption Reduction Real-time Signal Processing Sawtooth Transform Semiconductor Integrated Circuit Design Semiconductor Laboratory Cell Library Signal Processing Signal Processing And Detection Simulation Phase Size 180 Nm Smoothing Module SpLine Traditional Cubic Spline Interpolation Verilog-HDL Code Xilinx Vivado
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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