NDLI: 5 Gbit/s 2-tap low-swing voltage-mode transmitter with least segmented voltage-mode equalisation

Content Provider	IET Digital Library
Author	Kwak, Kang Sub Hong, Seong Kwan Kwon, Oh Kyong
Abstract	A 2-tap low-swing voltage-mode transmitter which compensates the loss of channel at high frequency is proposed. The output driver of the proposed 2-tap transmitter consists of only two voltage-mode drivers, and thereby the design complexity of the pre-driver is greatly reduced compared with that of conventional 2 N -segmented voltage-mode drivers, where N is the number of equalisation control bits. The output impedance of each voltage-mode driver is adjusted not only to make the overall output impedance matched with the characteristic impedance of the channel, but also to achieve the desired equalisation coefficient by adopting the proposed calibration circuitry. With a high equalisation coefficient, the proposed output driver consumes less power compared with the hybrid voltage-mode driver with current-mode equalisation. The proposed transmitter is implemented using a 90 nm low-power CMOS process technology and achieves 0.79 pJ/bit without equalisation and 0.98 pJ/bit with 6 dB equalisation, at the data rate of 5 Gbit/s.
Starting Page	1371
Ending Page	1373
Page Count	3
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 19, Sep (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/19
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2014.2285
Journal	Electronics Letters
Publisher	The Institution of Engineering and Technology
Publisher Date	2014-09-01
Access Restriction	Open
Rights License	Creative Commons Attribution-Non Commercial-No Derivs License (http://creativecommons.org/licenses/by-nc-nd/3.0/)
Subject Keyword	2-tap Low-swing Voltage-mode Transmitter Bit Rate 5 Gbit/s Calibration Circuitry Channel Characteristic Impedance Channel Loss Compensation CMOS Analogue Integrated Circuit CMOS Integrated Circuit Conventional 2N-segmented Voltage-mode Drivers Current-mode Equalisation Driver Circuit Equalisation Coefficient Equalisation Control Bits Equaliser Hybrid Voltage-mode Driver Impedance Matching Least Segmented Voltage-mode Equalisation Low Power Electronics Low-power CMOS Process Technology Power Electronics Power Supply Pre-driver Design Complexity Radio Link And Equipment Size 90 Nm Supervisory Circuit Transmitter
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

2-tap pre-emphasis SST transmitter with skin effect loss equalisation in 65 nm CMOS technology

12 Gbit/s three-tap FFE half-rate transmitter with low jitter clock buffering scheme

0.5–4.4 Gbit/s PAM4/NRZ dual-mode transceiver with 0.6 V near-ground NMOS driver for low-power memory interface

Single-ended voltage-mode duobinary transmitter with feedback time reduced parallel precoder

2 × 3.2 Gb/s single-ended IO transmitter with low-power dynamic FIR driver for the LPDDR4 standard

0.058 mm2 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss

Voltage-mode PAM4 driver with differential ternary R-2R DAC architecture

Single-ended 2 ch. × 3.4 Gbit/s dual-mode near-ground transmitter IO driver in 45 nm CMOS process

5–20 Gbit/s adaptive CTLE with spectrum balancing method

5 Gbit/s 2-tap low-swing voltage-mode transmitter with least segmented voltage-mode equalisation

Similar Documents

2-tap pre-emphasis SST transmitter with skin effect loss equalisation in 65 nm CMOS technology

12 Gbit/s three-tap FFE half-rate transmitter with low jitter clock buffering scheme

0.5–4.4 Gbit/s PAM4/NRZ dual-mode transceiver with 0.6 V near-ground NMOS driver for low-power memory interface

Single-ended voltage-mode duobinary transmitter with feedback time reduced parallel precoder

2 × 3.2 Gb/s single-ended IO transmitter with low-power dynamic FIR driver for the LPDDR4 standard

0.058 mm2 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss

Voltage-mode PAM4 driver with differential ternary R-2R DAC architecture

Single-ended 2 ch. × 3.4 Gbit/s dual-mode near-ground transmitter IO driver in 45 nm CMOS process

5–20 Gbit/s adaptive CTLE with spectrum balancing method

5 Gbit/s 2-tap low-swing voltage-mode transmitter with least segmented voltage-mode equalisation