NDLI: Zero bit error rate ID generation circuit using via formation probability in 0.18 μm CMOS process

Content Provider	IET Digital Library
Author	Kim, T. W. Choi, B. D. Kim, D. K.
Abstract	An integrated circuit for a physical unclonable function (PUF) to generate an identifier for each device is proposed based on the via formation probability. The via hole size is determined to be smaller than that specified by the design rule which guarantees successful via formation. As a result, a via is formed with a certain probability. A proper via hole size and a post-processing method are found to obtain very high randomness in the bit sequences, and it is confirmed that the bit error rate is zero through repeated measurements over one year under the supply voltage variations with noises and in a wide range of temperature. This time invariance of bits can be attributed to the fact that the via formation does not change over time, once they are formed.
Starting Page	876
Ending Page	877
Page Count	2
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 12, Jun (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/12
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2013.3474
Journal	Electronics Letters
Publisher Date	2014-05-28
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Bit Error Rate CMOS Integrated Circuit CMOS Process Design Rule Error Statistics ID Generation Circuit Integrated Circuit Design Integrated Circuit Interconnections Layout Metallisation And Interconnection Technology Modelling And Testing Physical Unclonable Function Probability Semiconductor Integrated Circuit Design Size 0.18 Mum Statistics Supply Voltage Variations Time Invariance Via Formation Probability Via Hole Size
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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