NDLI: Chip package interaction: A stress analysis on 3D IC's packages

Content Provider	IEEE Xplore Digital Library
Author	Lofrano, M. Gonzalez, M. Wei Guo Van der Plas, G.
Copyright Year	2015
Description	Author affiliation: imec, Leuven, Belgium (Lofrano, M.; Gonzalez, M.; Wei Guo; Van der Plas, G.)
Abstract	In this work CPI induced mechanical stress for 3D stacks and 3D interposer packages is studied. The stress built during package assembly has been obtained using finite element modeling (FEM). For the package layout and materials properties chosen for this work, the results shown that the stresses induced during the processing of a 3D stacks and 3D interposer configuration are similar when they are assembled in a Flip Chip Ball Grid Array (fcBGA) package. Furthermore, the interconnection between the different silicon dies assured with the use of μbumps were analyzed with different interconnect densities and configurations. Results shown that stress induced around the μbumps increases by increasing the μbump pitch. Different molding configurations for the fcBGA packages were investigated, including high power (exposed die) and low power (embedded dies) packages. The results showed that exposed die packages present lower out of plane deformation due to a reduction of the epoxy mold compound (EMC) thickness. It is very important to accurately calculate the residual stresses that each processing steps of the assembly induced on the die. Mass reflow and thermo compression bonding process assembly have been investigated. Results showed that solder joint reflow is the bottleneck for mass reflow process assembly, high stress in this step indicate that failures can occur. In this work we showed that low CTE laminate is a good alternative to reduce until 60% stress at flip chip reflow step.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	1
Ending Page	9
File Size	2305188
Page Count	9
File Format	PDF
e-ISBN	9781479999507
DOI	10.1109/EuroSimE.2015.7103096
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-04-19
Publisher Place	Hungary
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bonding Silicon Laminates Stress
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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