NDLI: SEU and SET Modeling and Mitigation in Deep Submicron Technologies

Content Provider	IEEE Xplore Digital Library
Author	Mavis, D.G. Eaton, P.H.
Copyright Year	2007
Description	Author affiliation: Microelectron. Res. Dev. Corp., Albuquerque, NM (Mavis, D.G.; Eaton, P.H.)
Abstract	As technology feature sizes decrease, single event upset (SEU), digital single event transient (DSET), and multiple bit upset (MBU) effects dominate the radiation response of microcircuits. Recent test circuits and test methods have quantified the pulse widths of DSETs generated from heavy-ion strikes on critical microcircuit nodes. These pulse widths have proven to be much larger than previously thought, which substantiates the importance of DSET induced errors to the soft error rate (SER) of modern microcircuits. New DSET circuit modeling approaches are presented which couple the circuit response to the charge collection mechanisms responsible for forming the DSET. These new circuit charge collection models successfully account for the experimentally observed heavy-ion induced transient widths and are supported by fully-coupled 3-d device physics simulations. Novel hardening and mitigation approaches are proposed based on our new understanding of the circuit response mechanisms. These new techniques are non-invasive to existing fabrication processes and can be transparently applied to existing bulk CMOS microcircuit layouts.
Starting Page	293
Ending Page	305
File Size	738268
Page Count	13
File Format	PDF
ISBN	1424409187
DOI	10.1109/RELPHY.2007.369907
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Single event upset Space vector pulse width modulation Pulse circuits Pulse generation Error analysis Coupling circuits Physics Circuit simulation Fabrication DSET Soft error SER radiation hardening upset SEU transient
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Test circuit for measuring pulse widths of single-event transients causing soft errors

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

Effect of Voltage Fluctuations on the Single Event Transient Response of Deep Submicron Digital Circuits

Analysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies

Test Circuit for Measuring Pulse Widths of Single-Event Transients Causing Soft Errors

SEE characterization and mitigation in ultra-deep submicron technologies

Role of the deep parasitic bipolar device in mitigating the single event transient phenomenon

Effect of multiple-transistor charge collection on SET pulse widths

The effect of elevated temperature on digital single event transient pulse widths in a bulk CMOS technology

SEU and SET Modeling and Mitigation in Deep Submicron Technologies

Similar Documents

Test circuit for measuring pulse widths of single-event transients causing soft errors

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

Effect of Voltage Fluctuations on the Single Event Transient Response of Deep Submicron Digital Circuits

Analysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies

Test Circuit for Measuring Pulse Widths of Single-Event Transients Causing Soft Errors

SEE characterization and mitigation in ultra-deep submicron technologies

Role of the deep parasitic bipolar device in mitigating the single event transient phenomenon

Effect of multiple-transistor charge collection on SET pulse widths

The effect of elevated temperature on digital single event transient pulse widths in a bulk CMOS technology

SEU and SET Modeling and Mitigation in Deep Submicron Technologies