NDLI: On The Interaction of ESD, NBTI and HCI in 65nm Technology

Content Provider	IEEE Xplore Digital Library
Author	Mishra, R. Mitra, S. Gauthier, R. Ioannou, D.E. Kontos, D. Chatty, K. Seguin, C. Halbach, R.
Copyright Year	2007
Description	Author affiliation: George Mason Univ., Fairfax, VA (Mishra, R.)
Abstract	A comprehensive study on the interaction between ESD, NBTI and HCI on silicide blocked (SBLK) PFET devices is presented for a state-of-the-art 65nm bulk technology. ESD behavior of thin and thick oxide devices are shown to have opposite channel length dependence. The study of NBTI-ESD interaction on thin oxides devices shows that non-destructive ESD pre-stressing worsens the NBTI degradation. On the other hand NBTI pre-stressed thick oxide devices show high on-resistance during ESD characterization. It is shown that in thin oxide long channel length devices at high temperature pure NBTI is the worst case degradation mode whereas in short channel length devices combined "HC-NBTI" degradation dominates. Furthermore, we observed that while a SBLK PFET is HC stressed at high temperature then NBTI also takes place simultaneously, resulting in "HC-NBTI" co-activation, which is found to be channel length dependent. Finally, we have shown that HC degradation is worse at high temperature than at room temperatures due to this NBTI co-activation.
Starting Page	17
Ending Page	22
File Size	312608
Page Count	6
File Format	PDF
ISBN	1424409187
DOI	10.1109/RELPHY.2007.369862
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electrostatic discharge Niobium compounds Titanium compounds Human computer interaction Degradation Stress Silicides Temperature dependence Hot carriers Driver circuits Interaction ESD NBTI HCI
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

The impact of NBTI and HCI on deep sub-micron PMOSFETs' lifetime

Process dependence of hot carrier degradation in PMOSFETS

NBTI and Concurrent HCI-NBTI Degradation of 65 nm SOI PMOSFETs

Mechanism and Modeling of PMOS NBTI Degradation with Drain Bias

Interaction of NBTI with Hot Carriers in PMOSFET's for Advanced CMOS Technologies

Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs

Unified Perspective of NBTI and Hot-Carrier Degradation in CMOS using on-the-Fly Bias Patterns

NBTI mechanism explored on the back gate bias for pMOSFETs

New Observations on the Hot Carrier and NBTI Reliability of Silicon Nanowire Transistors

On The Interaction of ESD, NBTI and HCI in 65nm Technology

Similar Documents

The impact of NBTI and HCI on deep sub-micron PMOSFETs' lifetime

Process dependence of hot carrier degradation in PMOSFETS

NBTI and Concurrent HCI-NBTI Degradation of 65 nm SOI PMOSFETs

Mechanism and Modeling of PMOS NBTI Degradation with Drain Bias

Interaction of NBTI with Hot Carriers in PMOSFET's for Advanced CMOS Technologies

Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs

Unified Perspective of NBTI and Hot-Carrier Degradation in CMOS using on-the-Fly Bias Patterns

NBTI mechanism explored on the back gate bias for pMOSFETs

New Observations on the Hot Carrier and NBTI Reliability of Silicon Nanowire Transistors

On The Interaction of ESD, NBTI and HCI in 65nm Technology