NDLI: Study of Plasma Damage at Recess-Channel Gate (RG) Structure During Plasma Nitridation

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Table of contents

Basic Research for the Air Force of the 21st Century

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Call for papers and call for posters

On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy?

Estimation of NBTI Degradation using IDDQ Measurement

On The Interaction of ESD, NBTI and HCI in 65nm Technology

SRAM Variability and Supply Voltage Scaling Challenges

Quantitative Analysis of Random Telegraph Signals as Fluctuations of Threshold Voltages in Scaled Flash Memory Cells

Dielectric Breakdown in High-K Gate Dielectrics - Mechanism and Lifetime Assessment

New Understanding on the Breakdown of High-K Dielectric Stacks using Multi-Vibrational Hydrogen Release Model

Progressive Breakdown Characteristics of High-K/Metal Gate Stacks

Defects Generation in SIO2/HFO2 Studied with Variable TCHARGE-TDIScharge Charge Pumping (VT2CP)

In Depth Analysis of VT Instabilities in HFO2 Technologies by Charge Pumping Measurements and Electrical Modeling

Comparison of Plasma-Induced Damage in SIO2/TIN and HFO2/TIN Gate Stacks

Kinetic Analysis of X-Ray Irradiation Induced Static Refresh Failure Mechanism in DRAM

Macro-Model for Post-Breakdown 90NM and 130NM Transistors and its Applications in Predicting Chip-Level Function Failure after ESD-CDM Events

Degradation Mechanisms in CMOS Power Amplifiers Subject to Radio-Frequency Stress and Comparison to the DC Case

Realistic Projections of Product Fmax Shift and Statistics due to HCI and NBTI

The Impact of Ball-Bonding Induced Voltage Transient on Sub-90nm CMOS Technology

On the Physics of Failure in the Case of Moisture Induced Delamination in Plastic Encapsulated Microelectronic Devices

Identification of Brittle Solder Joints using High Strain Rate Testing of BGA Solder Joints

A Study on Wire Ball/Pad Open Failure Mechanism of a Multi-Stack Package (MSP) under High Temperature Storage (HTS) Condition

Analytical Study of Impurity Doping Effects on Electromigration of CU Interconnects by Employing Comprehensive Scattering Model

Plasticity-Amplified Diffusivity: Dislocation Cores as Fast Diffusion Paths in CU Interconnects

Cu Interconnect Width Effect, Mechanism and Resolution on Down-Stream Stress Electromigration

Design for Manufacturability and its Role in Enhancing Stress Migration Reliability of Porous Ultra Low-k Copper Interconnects

SiGe BiCMOS Technology: An IC Design Platform for Extreme Environment Electronics Applications

Understanding Tin Plasmas: A New Approach to Tin Whisker Risk Assessment

Cryogenic Reliability Impact on Analog Circuits at Extreme Low Temperatures

Statistical Investigation of Random Telegraph Noise ID Instabilities in Flash Cells at Different Initial Trap-filling Conditions

Effects of Lateral Charge Spreading on the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory

Reliability and Processing Effects of Bandgap Engineered SONOS (BE-SONOS) Flash Memory

A Novel Gate-Sensing and Channel-Sensing Transient Analysis Method for Real-Time Monitoring of Charge Vertical Location in Sonos-Type Devices and its Applications in Reliability Studies

Development and Optimization of Re-Oxidized Tunnel Oxide with Nitrogen Incorporation for the Flash Memory Applications

Influence of Hydrogen Permeability of Liner Nitride Film on Program/Erase Endurance of Split-Gate Type Flash EEPROMS

The Current Understanding of the Trap Generation Mechanisms that Lead to the Power Law Model for Gate Dielectric Breakdown

Quantum Mechanical Treatment of Si-O Bond Breakage in Silica Under Time Dependent Dielectric Breakdown Testing

Lifetime Prediction for CMOS Devices with Ultra Thin Gate Oxides Based on Progressive Breakdown

Significance of Breakdown Location on Post-Breakdown Transient and MOSFET Degradation

Reconsideration of Hydrogen-Related Degradation Mechanism in Gate Oxide

Analytic Extension of the Cell-Based Oxide Breakdown Model to Full Percolation and its Implications

Defects in Organic Molecular Crystals: Spectroscopy and Effects on Electronic and Optical Properties

Bias Stress Effects in Organic Thin Film Transistors

Mechanisms of Operation and Degradation in Solution-Processable Organic Photovoltaics

OLED Device Operational Lifetime: Insights and Challenges

Ballistic phonon enhanced NBTI

Mechanism and Modeling of PMOS NBTI Degradation with Drain Bias

The Universality of NBTI Relaxation and its Implications for Modeling and Characterization

Correction of Self-Heating for HCI Lifetime Prediction

Consideration of recovery effects during NBTI measurements for accurate lifetime predictions of state-of-the-art pMOSFETs

SEU and SET Modeling and Mitigation in Deep Submicron Technologies

Single Event Upsets in a 130 nm Hardened Latch Design Due to Charge Sharing

Experimental Characterization and Application of Circuit Architecture Level Single Event Transient Mitigation

Random Dopant Effect on Vt Variations Affecting the Soft-Error Rates of Nanoscale CMOS Memory Cells

Survey on Very Fast TLP and Ultra Fast Repetitive Pulsing for Characterization in the CDM-Domain

Effects of Background Doping Concentration on ESD Protection Properties of High Voltage Operation Extended Drain N-Type MOSFET Device

Drain Extended NMOS High Current Behavior and ESD Protection Strategy for HV Applications in Sub-100nm CMOS Technologies

Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies

External Latchup Characteristics Under Static and Transient Conditions in Advanced Bulk CMOS Technologies

A Comprehensive Model for Plasma Damage Enhanced Transistor Reliability Degradation

Study of Plasma Damage at Recess-Channel Gate (RG) Structure During Plasma Nitridation

Impact of Bottom Interfacial Layer on the Threshold Voltage and Device Reliability of Fluorine Incorporated PMOSFETS with High-K/Metal Gate

Reliability Investigations for Bulk-FinFETs Implementing Partially-Insulating Layer

The Effect of Metal Area and Line Spacing on TDDB Characteristics of 45nm Low-k SiCOH Dielectrics

Modeling of Interconnect Dielectric Lifetime Under Stress Conditions and New Extrapolation Methodologies for Time-Dependent Dielectric Breakdown

Time Dependent Dielectric Breakdown Characteristics of Low-k Dielectric (SiOC) Over a Wide Range of Test Areas and Electric Fields

Moisture Related Low-K Dielectric Reliability Before and After Thermal Annealing

Role of CU in TDDB of Low-K Dielectrics

Effect of Scratch Stress on the Surface Hardness and Inner Structures of a Capacitive Fingerprint Sensor LSI

Time and voltage dependence of dielectric charging in RF MEMS capacitive switches

A Critical Enhancement in the Yield Analysis of Microsystems

Failure Mechanisms in MEMS Based Silicon Carbide High Temperature Pressure Sensors

Extended Reliability Study of High Density PZT Capacitors: Intrinsic Lifetime Determination and Wafer Level Screening Strategy

Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

Erratic Bit Errors in Latches

Understanding SRAM High-Temperature-Operating-Life NBTI: Statistics and Permanent vs Recoverable Damage

Reversible Degradation of GaN LEDs Related to Passivation

Ultra-Fast Characterization of Transient Gate Oxide Trapping in SiC Mosfets

Investigating the Stability of Thin Film Transistors with Zinc Oxide as the Channel Layer

Accelerated RF life Testing of Gan Hfets

Reliability Assessment of 1.55-μM Vertical Cavity Surface Emitting Lasers for Optical Communication Systems

Reliability of High-Power IGBT Modules for Traction Applications

Investigation and Improvement of Fast Temperature-Cycle Reliability for DMOS-Related Conductor Path Design

A Comprehensive Model for Hot Carrier Degradation in LDMOS Transistors

Photo Misalignment Impact on the Hot Carrier Reliability of Lateral DMOS Devices

Location, Structure, and Density of States of NBTI-Induced Defects in Plasma Nitrided pMOSFETs

Reliability Challenges in Copper Metallizations arising with the PVD Resputter Liner Engineering for 65nm and Beyond

High-Resolution Characterization of Ultra-Shallow Junctions by Scanning Spreading Resistance Microscopy

Picosecond Timing Analysis in Integrated Circuits with Pulsed Laser Stimulation

Investigation of Laser Voltage Probing Signals in CMOS Transistors

Phase Variation Mapping, a Dynamic Laser Stimulation Technique with Picosecond Timing Resolution

Data Retention Characterization of Phase-Change Memory Arrays

A Physics-Based Crystallization Model for Retention in Phase-Change Memories

A Highly Reliable FRAM (Ferroelectric Random Access Memory)

Novel Cycling-induced Program Disturb of Split Gate Flash Memory

An Efficient Certification Approach for New SN-AG-CU Solder Alloy

Themixed-Mode Damage Spectrum of Sige HBTs

Temperature and Voltage Dependent RF Degradation Study in Algan/gan HEMTs

Correlating Wafer-Level TDDB Lifetime Projections to HTOL Gate-Oxide Failures

The Role of Power Dissipation on the Progressive Breakdown Dynamics of Ultra-Thin Gate Oxides

A New "Multi-step" Power-law TDDB Lifetime Model and Boron Penetration Effect on TDDB of Ultra Thin oxide

A Critical Gate Voltage Triggering Irreversible Gate Dielectric Degradation

New Insights on Percolation Theory and the Origin of Oxide Breakdown Thickness and Process Deposition Dependence

Methodology for Word Line-Contact Dielectric Characterization in Flash Normemories

Reverse-Body Biasing for Radiation-Hard by Design Logic Gates

Power Performance Characteristics of SiGe Power HBTs at Extreme Temperatures

ESD Testing of Aluminum and Copper Vertical Parallel plate (VPP) Capacitor Structures

A Simple and Useful Layout Scheme to Achieve Uniform Current Distribution for Multi-Finger Silicided Grounded-Gate NMOS

Board Level ESD of Driver ICS on LCD Panels

Leakage Suppression of Low Voltage Transient Voltage Suppressor

Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes

Novel Robust High Voltage ESD Clamps for LDMOS Protection

Failure of On-Chip Power-Rail ESD Clamp Circuits During System-Level ESD Test

An Investigation of External Latchup

Mixed Device-Circuit Solution for ESD Protection of High-Voltage Fast pins

25V ESD NPN Transistor Optimized by Distributed Emitter Ballasting using Emitter Contact Area Segmentation

A Novel Method for Guard Ring Efficiency Assessment and its Applications for ESD Protection Design and Optimization

An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies

Limitation of WSix/WN Diffusion Barrier for Tungsten Dual Polymetal Gate Memory Devices

Failure Analysis of an Anomalous Subthreshold Current in Nano-Scale NAND Flash Memory

A New Method for Failure Analysis with Probing System Based on Scanning Electron Microscope

Failure Analysis and Optimization of Metal Fuses for Post Package Trimming

Maximum Permissible EB Acceleration Voltage for SEM-Based Inspection Before Electrical Characterization of Advanced MOS

Determination of Intrinsic Spectra from Frontside & Backside Photon Emission Spectroscopy

Investigation of hot carrier effects in n-MOSFETs thick oxide with HfSiON and SiON gate dielectrics

BTI and Electron Trapping in Hf-based Dielectrics with Dual Metal Gates

Hot Carrier Degradation of p-LDMOS Transistors for RF Applications

Leakage Current Characteristic of Pre-Damaged Interlayer Dielectric During Voltage Ramp Method

New Understanding of Metal-Insulator-Metal (MIM) Capacitor Degradation Behavior

Test Structure Design for Precise Understanding of Cu/Low-k Dielectric Reliability

Theoretical Analysis of Vacancy Transport Combined with Electromigration and Stress Induced Voiding

Characterization of Electromigration Parameters on Single Device

New Degradation Phenomena of Stress-Induced Voiding Inside via in Copper Interconnects

Characterization of Degradation of 65nm Node via Chains and Single Vias

On the Interaction Between Inter-Metal Dielectric Reliability and Electromigration Stress

Hybrid Grain-Continuum Model for Thermo-Mechanical Stresses in Polycrystalline Cu 3D IC Vias

Influence of Surface Cleaning on Stressvoiding and Electromigration of Cu Damascene Interconnection

Investigation of via Bottom Barrier Integrity Impact on Electromigration

Effect of Interface Buffer Layer on the Reliability of Ultra-Thin MgO Magnetic Tunnel Junctions for Spin Transfer Switching MRAM

Improving the Endurance Characteristics Through Boron Implant at Active Edge in 1 G NAND Flash

Hole Distributions in NROM Devices: Profiling Technique and Correlation to Memory Retention

Measurement Technique of Carrier Mobility in Silicon Nitride and its Application to Data Retention in MONOS Memories

Role of Oxide/Nitride Interface Traps on the Nanocrystal Memory Characteristics

Reliability Studies on Non Planar DRAM Cell Transistor

Reliability of a 90nm Embedded Multi-time Programmable Logic NVM Cells Using Work-function Engineered Tunneling Device

Impact of Gate Tunneling Leakage on Performances of Phase Locked Loop Circuit in Nanoscale CMOS Technology

Product Burn-in Stress Impacts on SRAM Array Performance

On the 6T-SRAM Cells Degradation Characterization in Ultra-Scaled CMOS Technologies

Improved Hot Carrier Reliability in Strained-Channel NMOSFETS with TEOS Buffer Layer

Effect of in situ plasma treatment on high-k films after high-k removal with plasma etching from the S/D region

High Pressure Deuterium Annealing Effect on Nano-Scale Strained CMOS Devices

Quantifying the Effectiveness of Guard Bands in Reducing the Collected Charge Leading to Soft Errors

A Quantitative Analysis of Neutron-Induced Multi-Cell Upset in Deep Submicron SRAMs and of the Impact Due to Anomalous Noise

The Influence of Gate Poly-Silicon Oxidation on Negative Bias Temperature Instability in 3D FinFET

Degradation Dependent on Channel Width in Sequential Lateral Solidified Poly-Si Thin Film Transistors

Hot Carrier Reliability of Strained N-Mosfet with Lattice Mismatched Source/Drain Stressors

Novel Positive Bias Temperature Instability (PBTI) of N-Channel Mosfets with Plasma Nitrided Oxide

The Impact of Nitrogen on the Frequency Dependence of Negative-Bias Temperature Instability

History Dependent Recovery of NBTI under Alternating DC and AC Stress

The Energy-Driven Hot Carrier Degradation Modes

An Investigation of Self-Heating Degradation of Metal Induced Laterally Crystallized N-Type Polysilicon Thin Film Transistors

Unified Perspective of NBTI and Hot-Carrier Degradation in CMOS using on-the-Fly Bias Patterns

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Study of Plasma Damage at Recess-Channel Gate (RG) Structure During Plasma Nitridation

Content Provider	IEEE Xplore Digital Library
Author	Heung-Jae Cho Tae-Yoon Kim Se-Aug Jang Hyun Ahn Yong Soo Kim Kwan-Yong Lim Min Gyu Sung Hong-Seon Yang Seung-Ho Pyi Jin Woong Kim
Copyright Year	2007
Description	Author affiliation: R&D Div., Hynix Semicond. Inc., Kyoungki-do (Heung-Jae Cho; Tae-Yoon Kim; Se-Aug Jang; Hyun Ahn; Yong Soo Kim; Kwan-Yong Lim; Min Gyu Sung; Hong-Seon Yang; Seung-Ho Pyi; Jin Woong Kim)
Abstract	The plasma induced damage of gate oxide was observed at the recess-channel gate (RG) transistor during the plasma nitridation, which is not observed at the 2-dimensional planar structure. The model of electron shading which is known as a topographical effect in plasma charging can explain the specific structure dependence of the plasma damage. The thinnest bottom gate oxide at the RG structure is found to be severe damaged by positive ions during the plasma nitridation
Starting Page	370
Ending Page	373
File Size	636162
Page Count	4
File Format	PDF
ISBN	1424409187
DOI	10.1109/RELPHY.2007.369917
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Roentgenium Transistors MOS capacitors Random access memory Boron Nitrogen Design for quality Plasma properties Fluid flow Silicon
Content Type	Text
Resource Type	Article

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