NDLI: DESSERT: DESign Space ExploRation Tool based on power and energy at System-Level

Content Provider	IEEE Xplore Digital Library
Author	Kumar Rethinagiri, S. Palomar, O. Cristal, A. Unsal, O. Swift, M.M.
Copyright Year	2014
Description	Author affiliation: Univ. of Wisconsin-Madison, Madison, WI, USA (Swift, M.M.) \|\| BSC-Microsoft Res. Center, Spain (Kumar Rethinagiri, S.; Palomar, O.; Cristal, A.; Unsal, O.)
Abstract	This paper proposes DESSERT (DESign Space ExploRation Tool at System-Level), a novel simulation-based tool for heterogeneous multi-core processor based platforms. This tool supports power/energy estimation, comprehensive architectural explorations and optimization of the given embedded applications for multi-core processor architectures. The development of DESSERT consists of three steps. First, we developed generic functional-level power models for different parts of the multi-core system to estimate power/energy, which are integrated into the system-level simulation environment. Second, we built a SystemC-based virtual platform prototype of the processor architecture to accurately extract the functional activities needed by the power model. Third, we designed a runtime task-dependencies management and optimization technique (work-load or dynamic slack reclamation) based on programming models that support both OpenMP and Pthread API for multi-core execution to consider both data-level and thread-level parallelism. The combination of above three steps leads to a novel Design Space Exploration (DSE) methodology. Power and energy estimates are validated against real board measurements. DESSERT power/energy estimation results provide less than 5% of error and offer reliable power/energy based DSE for the given applications.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	48
Ending Page	53
File Size	1792533
Page Count	6
File Format	PDF
ISBN	9781479933785
ISSN	21641706
DOI	10.1109/SOCC.2014.6948898
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Space exploration Program processors Reliability Power measurement Process control Frequency control Kalman filters
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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