NDLI: A clock generator based on multiplying delay-locked loop

Content Provider	IEEE Xplore Digital Library
Author	Chorng-Sii Hwang Ting-Li Chu Wen-Cheng Chen
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. Eng., Nat. Yunlin Univ. of Sci. & Technol., Yunlin, Taiwan (Chorng-Sii Hwang; Wen-Cheng Chen) \|\| Grad. Sch. of Eng. Sci. & Technol., Nat. Yunlin Univ. of Sci. & Technol., Yunlin, Taiwan (Ting-Li Chu)
Abstract	This paper presents a clock generator based on multiplying delay-locked loop (MDLL). With the aid of the frequency detector and the improved select logic circuitry, the clock generator can perform the lock-in process and the edge-selecting function correctly. It also provides the capability of the frequency switching like the conventional PLL-based clock generators without any external control signal. The test chip is designed and fabricated in TSMC 0.18 μm CMOS process. The core circuitry occupies an area of 0.06 $mm^{2}$ and consumes the power of 22.4 mW at the output frequency of 1.19 GHz. The measured peak-peak jitter is 19.2 ps.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	98
Ending Page	102
File Size	1494664
Page Count	5
File Format	PDF
ISBN	9781479933785
ISSN	21641706
DOI	10.1109/SOCC.2014.6948907
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Detectors Delays Generators Phase frequency detector Charge pumps select logic multiplying delay-locked loop (MDLL) frequency detector
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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