NDLI: Hypermedia processors: design space exploration

Content Provider	IEEE Xplore Digital Library
Author	Kin, J. Chunho Lee Mangione-Smith, W.H. Potkonjak, M.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA (Kin, J.)
Abstract	We present a framework for area optimal system design space exploration for hypermedia applications. We focus on a category of processors that are programmable yet optimized to a hypermedia application. The key components of the framework presented in this paper are a retargetable instruction-level parallelism compiler, instruction level simulators, a set of complete media applications written in a high level language and a media processor synthesis algorithm. The framework addresses the need for area optimal system design by exploiting the instruction-level parallelism found in media applications by compilers that target multiple-instruction-issue processors. Using the framework we conduct an extensive exploration of area optimal system design space for a hypermedia application. We found that there is enough ILP in the typical media and communication applications to achieve highly concurrent execution when throughput requirements are high. On the other hand, when throughput requirements are low, there is no need to use multiple-instruction-issue processors.
Starting Page	323
Ending Page	328
File Size	408115
Page Count	6
File Format	PDF
ISBN	0780349199
DOI	10.1109/MMSP.1998.738954
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-12-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Process design Space exploration Space technology Throughput Application software Parallel processing High level languages Collaborative work Program processors Microprocessors
Content Type	Text
Resource Type	Article

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