NDLI: A neural rehabilitation chip with neural recording, peak detection, spike rate counter, and biphasic neural stimulator

Content Provider	IEEE Xplore Digital Library
Author	Hongjiang Song Chen Chen Meng-Wei Lin Kaijun Li Christen, J.B.
Copyright Year	2014
Description	Author affiliation: Sch. of Electr., Comput., & Energy Eng., Arizona State Univ., Tempe, AZ, USA (Hongjiang Song; Chen Chen; Meng-Wei Lin; Kaijun Li; Christen, J.B.)
Abstract	We demonstrate an integrated circuit to be used as a neural prosthetic. The circuit is designed to record and amplify neural signals. The amplified neural signals are fed through to a sigma-delta analog to digital converter. The output of the sigma-delta is used to control the frequency of a voltage controlled oscillator circuit. The resulting signal is the output of the circuit to be transmitted wirelessly in the next version of the chip. In addition, the amplified neural signal is introduced to a peak detection circuit. The interval between detected peaks is determined and used to trigger a biphasic neural stimulation circuit. The chip is intended as a rehabilitation device for patients suffering from traumatic brain injury or stroke. The chip detect the signals near the damaged area of the brain and reroute the signals to healthy neurons. Our goal is to enable rehabilitation through rerouting and reprogramming of the brain to take advantage of neural plasticity. The chip was implemented in a standard 0.5 μm CMOS process.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	415
Ending Page	419
File Size	1221605
Page Count	5
File Format	PDF
ISBN	9781479933785
ISSN	21641706
DOI	10.1109/SOCC.2014.6948965
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radiation detectors Voltage-controlled oscillators Electric potential Frequency control Detectors Layout Analog-digital conversion
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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