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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Grandhi, S. Spagnol, C. Jiaoyan Chen Popovici, E. Cotafona, S. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Electr. & Electron. Eng., Univ. Coll. Cork, Cork, Ireland (Grandhi, S.; Spagnol, C.; Jiaoyan Chen; Popovici, E.) || Fac. of EE, Math. & CS, Delft Univ. of Technol., Delft, Netherlands (Cotafona, S.) |
| Abstract | The low reliability of advanced CMOS devices has become a critical issue that has to be considered in the digital IC design flow. This paper introduces a design time methodology to address and improve the reliability of combinational circuits. The key idea is to employ local transformation rules, a methodology that were extensively used for area, delay, and power optimizations and demonstrate that they can reduce the error probability as well.We propose a set of local transformation rules that enhance the reliability without altering the circuit functionality. This functional rewriting capability, along with a circuit reliability assessment methodology developed in house, enables the integration of the reliability aware analysis and logic optimization algorithm that iteratively transforms the design in order to achieve higher circuit reliability. Experimental results based on simulations performed on MCNC benchmark circuits indicate that method can provide a reliability improvement of up to 7.5%. |
| Sponsorship | IEEE Circuits Syst. Soc. |
| Starting Page | 274 |
| Ending Page | 279 |
| File Size | 628671 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479933785 |
| ISSN | 21641706 |
| DOI | 10.1109/SOCC.2014.6948940 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-09-02 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuit reliability Logic gates Error probability Optimization Benchmark testing Simulation Rewriting And-Invert Graphs (AIG) ABC Tool Local Transformation Rules Reliability Synthesis |
| Content Type | Text |
| Resource Type | Article |
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