NDLI: MITH-Dyn: A multi V dynamic logic design style using mixed mode FinFETs

Content Provider	IEEE Xplore Digital Library
Author	Nair, R. Vemuri, R.
Copyright Year	2014
Description	Author affiliation: Dept. of EECS, Univ. of Cincinnati, Cincinnati, OH, USA (Nair, R.; Vemuri, R.)
Abstract	In FinFETs, the back-gate of the transistor can be biased to control its $V_{th},$ thereby reducing leakage power at the expense of performance. This paper proposes a novel multi $V_{th}$ dynamic logic design style (MITH-Dyn) which reduces the leakage power without degrading performance. MITH-Dyn has been tested on dynamic circuits of varying design complexity in both domino logic and np zipper logic. We report leakage savings of 90.83%, 89.14% and total power savings of 36.7%, 32.2% for domino circuits and np zipper circuits respectively. MITH-Dyn has also been extended to $C^{2}FinFET$ based latches and registers and also to NORA (No Race) FinFET based pipeline circuits. Total power savings of 27.98% and 36.16% was obtained for 2-stage and 4-stage NORA pipeline circuits respectively. We have used the 45nm FinFET model cards from PTM [1] for all the results reported in this paper.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	140
Ending Page	145
File Size	1027112
Page Count	6
File Format	PDF
ISBN	9781479933785
ISSN	21641706
DOI	10.1109/SOCC.2014.6948915
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Logic gates Clocks CMOS integrated circuits Pipelines Power demand leakage power multi Vth dynamic logic
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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