NDLI: A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Chi-Hao Hong Yi-Wei Chiu Jun-Kai Zhao Shyh-Jye Jou Wen-Tai Wang Lee, R.
Copyright Year	2014
Description	Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Chi-Hao Hong; Yi-Wei Chiu; Jun-Kai Zhao; Shyh-Jye Jou) \|\| Global Unichip Corp., Hsinchu, Taiwan (Wen-Tai Wang; Lee, R.)
Abstract	In this paper, we propose an architecture for low power SRAM designs by using hierarchical bitlines for SRAM macros with the charge sharing Read technique. Moreover, sense amplifiers are important circuits for accessing the data from internal storage nodes to data outputs. We compare two types of sense amplifiers, a current-latched sense amplifier (CLSA) and a voltage-latched sense amplifier (VLSA), and focus on the characteristics of input offset voltages and power consumption in 28 nm HPM CMOS technology. Detailed post-layout simulations with Monte Carlo mismatch model are utilized to compare the two structures. From our analysis and implementation results, using the pass-gate based hierarchical bitline with the charge sharing Read scheme gains at least 59% and 66% LBL/GBL power reduction for a 2-bank and a 4-bank hierarchical architectures at five corners, respectively. VLSA performs lower input offset voltage, higher speed and lower power consumption as compared to CLSA. The proposed combination of the pass-gate based hierarchical bitline with the charge sharing Read scheme and VLSA is suitable for SRAM macros with the high-speed and low-power design considerations.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	160
Ending Page	164
File Size	845112
Page Count	5
File Format	PDF
ISBN	9781479933785
ISSN	21641706
DOI	10.1109/SOCC.2014.6948919
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Power demand Simulation CMOS integrated circuits Arrays Sensors CMOS technology charge sharing SRAM current-latched sense amplifier voltage-latched sense amplifier low power hierarchical bitline
Content Type	Text
Resource Type	Article

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