NDLI: Experimental analysis of read related transistors’ gate width sizing effects on the 3T1D DRAM access time curve

Content Provider	IEEE Xplore Digital Library
Author	Lorenzo, M.A.G. Tan, W.M. Ballesil, A.P. Alarcon, L.P.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. & Electron. Eng., Univ. of the Philippines at Diliman, Quezon (Lorenzo, M.A.G.; Tan, W.M.; Ballesil, A.P.) \|\| Dept. of Electr. Eng. & Comput. Sci., Univ. of California at Berkeley, Berkeley, CA (Alarcon, L.P.)
Abstract	Unlike SRAMs, the access time of 3T1D DRAMs increase as the feature size becomes smaller. To combat this slow down, it has been suggested that the sizes of read related transistors be increased, a technique that has never been thoroughly explored. This paper deals with the exploration of the effects of the said technique, focusing on its effectiveness as a function of the width increase and how it holds up as feature sizes get smaller. Our results show that applying such technique sometimes has unexpected and surprising effects, including deviating the access time curve from its expected shape, and worse, even slowing the memory cell down even further at certain times-of-read. We also discovered that the effectiveness of the technique actually becomes more and more limited as feature sizes get smaller. At a smaller feature size, it would no longer be sufficient by itself, and would have to be combined with another technique to speed up the memory cell.
Starting Page	450
Ending Page	454
File Size	863647
Page Count	5
File Format	PDF
ISBN	9781424438730
DOI	10.1109/SMELEC.2008.4770361
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-25
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Diodes Voltage Capacitance Predictive models Transistors Shape DRAM chips SRAM chips Analytical models
Content Type	Text
Resource Type	Article

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