NDLI: Low power ROM employing dynamic threshold-voltage MOSFET (DTMOS) technique

Content Provider	IEEE Xplore Digital Library
Author	Mustapa, M. Mohd-Yasin, F. Khawi, M.K. Reaz, M.B.I. Kordesch, A.
Copyright Year	2008
Description	Author affiliation: Fac. of Eng., Multimedia Univ., Cyberjaya (Mustapa, M.; Mohd-Yasin, F.; Khawi, M.K.) \|\| Int. Islamic Univ., Gombak (Reaz, M.B.I.) \|\| Device Modeling Dept., Silterra, Kulim (Kordesch, A.)
Abstract	This paper examines the performance of two 128-bit ROM circuits, implemented on Silterra 0.18 u CMOS process. The first circuit is built using standard NMOS transistors, runs on 0.9 V supply voltage, has gate voltage of 0.45 V and consumes 102.07 muW power. The second circuit is designed partly using Dynamic Threshold-Voltage MOSFET (DTMOS) transistors with the aim to minimize power consumption. It runs on 0.7 V supply and has gate voltage of 0.35 V. The DTMOS approach is implemented on the 128-bit ROM core and in the pull up circuit of the column decoder. The latter ROM circuitpsilas power consumption is 38.93 muW, 61.86% less than the former, at the expenses of larger die area due to the usage of deep n-well process. The standard and DTMOST circuits have the die areas of 0.139 mum2 and 0.235 mum2, respectively.
Starting Page	103
Ending Page	107
File Size	2263577
Page Count	5
File Format	PDF
ISBN	9781424438730
DOI	10.1109/SMELEC.2008.4770286
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-25
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Read only memory MOSFET circuits Power MOSFET Energy consumption Threshold voltage Low voltage MOS devices CMOS process Batteries Photonic band gap
Content Type	Text
Resource Type	Article

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