NDLI: A 64 Kbit MOS dynamic RAM with novel memory capacitor

Content Provider	IEEE Xplore Digital Library
Author	Smith, F.J. Yu, R.T. Lee, I. Wong, S.-W.S. Embrathiry, M.P.
Copyright Year	1966
Description	A 64 Kbit dynamic RAM is described. The RAM features a novel memory cell using a polysilicon-dielectric-polysilicon (PDP) capacitor. This structure provides performance and density advantages over the conventional approaches. A new sense amplifier configuration is also described in detail. It multiplexes two pairs of bit lines for each sense amplifier. Thus the number of memory cells per bit line is halved. This reduces the length of each bit line, thereby increasing the signal voltage available to the sense amplifier. A compatible dummy cell design is included in the discussion. Using conservative processing (3.5 /spl mu/m device channel length with 700 /spl Aring/ gate oxide thickness) a die size of 3.2 mm/spl times/7.9 mm is achieved. Experimental data are presented in the text.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	184
Ending Page	189
Page Count	6
File Size	1180119
File Format	PDF
ISSN	00189200
Volume Number	15
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1980-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	DRAM chips Random access memory MOS capacitors Switches Read-write memory Voltage Transistors Capacitance Contacts
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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